700MHz, Low Jitter, Crystal-To-3.3V
LVPECL Frequency Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (84330CV-01)
84330-01
DATA SHEET
General Description
The 84330-01 is a general purpose, single output high frequency
synthesize. The VCO operates at a frequency range of 250MHz to
700MHz. The VCO and output frequency can be programmed using
the serial or parallel interfaces to the configuration logic. The output
can be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps from 250kHz to 2MHz can be achieved using
a 16MHz crystal depending on the output divider setting.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz – 25MHz
Output frequency range: 31.25MHz – 700MHz
VCO range: 250MHz – 700MHz
Parallel or serial interface for programming M and N dividers
during power-up
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 8T49N242
Block Diagram
XTAL_IN
OSC
XTAL_OUT
Pin Assignments
÷ 16
PLL
PHASE DETECTOR
1
VCO
÷M
÷2
0
÷1
÷2
÷4
÷8
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
V
EE
TEST
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL_OUT
XTAL_IN
nc
nc
V
CCA
S_LOAD
S_DATA
S_CLOCK
V
CCO
FOUT
nFOUT
V
EE
FOUT
nFOUT
84330-01
28 Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
nFOUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
V
CCO
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
V
CCA
nc
nc
XTAL_IN
26
27
17
28 Lead PLCC
28
11.5mm x 11.5mm x 4.4mm
16
package body
15
1
V Package
Top View
14
2
3
4
5
XTAL_OUT
M2
V
CC
nP_LOAD
M0
84330-01 Rev A 5/26/16
1
©2016 Integrated Device Technology, Inc.
M1
M3
FOUT
TEST
V
CC
84330-01
V
EE
V
EE
18
N1
N0
M8
M7
M6
M5
M4
13
12
6
7
8
9
10 11
84330-01 DATA SHEET
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The 84330-01 features a fully integrated PLL and therefore requires
no external components for setting the loop bandwidth. A
parallel-resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal, this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the 84330-01 support two input
modes and to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1
shows the
timing diagram for each mode. In parallel mode, the nP_LOAD input
is initially LOW. The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On the
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. The TEST output is Mode
000 (shift register out) when operating in the parallel input mode. The
relationship between the VCO frequency, the crystal frequency and
the M divider is defined as follows:
fVCO = fXTAL x 2M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock are defined as
125
M
350.
The frequency out is defined as follows:
fout = fVCO = fXTAL x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched
on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider on each
rising edge of S_CLOCK. The serial mode can be used to program
the M and N bits and test bits T2:T0. The internal registers T2:T0
determine the state of the TEST output as follows in the table below:
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N Divider
fOUT
TEST Output
Shift Register Out
HIGH
PLL Reference XTAL ÷16
(VCO ÷ M) /2 (non 50% Duty Cycle M Divider)
fOUT, LVCMOS Output Frequency < 200MHz
LOW
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M Divider)
fOUT ÷ 4
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T2
S
T1
H
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
nP_LOAD
Time
Figure 1. Parallel & Serial Load Operations
Rev A 5/26/16
2
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
84330-01 DATA SHEET
Table 1. Pin Descriptions
Name
M0, M1, M2, M3, M4,
M5, M6, M7, M8
N0, N1
V
EE
TEST
V
CC
FOUT, nFOUT
V
CCO
nc
S_CLOCK
S_DATA
S_LOAD
V
CCA
XTAL_IN
XTAL_OUT
nP_LOAD
Input
Input
Power
Output
Power
Output
Power
Unused
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Type
Pullup
Pullup
Description
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
Determines output divider value as defined in Table 3C, Function Table.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output pair for the synthesizer. LVPECL interface levels.
Output supply pin for LVPECL outputs.
No connect.
Clocks the serial data present at S_DATA input into the shift register on the rising edge of
S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divider value.
LVCMOS/LVTTL interface levels.
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
3
Rev A 5/26/16
84330-01 DATA SHEET
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD
X
L
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
L
H
S_CLOCK
X
X
X
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until next
LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA
on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
= Rising edge transition
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
700
256
M Divide
125
126
127
128
•
•
348
349
350
M8
0
0
0
0
•
•
1
1
1
128
M7
0
0
0
1
•
•
0
0
0
64
M6
1
1
1
0
•
•
1
1
1
32
M5
1
1
1
0
•
•
0
0
0
16
M4
1
1
1
0
•
•
1
1
1
8
M3
1
1
1
0
•
•
1
1
1
4
M2
1
1
1
0
•
•
1
1
1
2
M1
0
1
0
1
•
•
0
0
1
1
M0
1
0
1
0
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
Rev A 5/26/16
4
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
84330-01 DATA SHEET
Table 3C. Programmable Output DividerFunction Table
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
2
4
8
1
Output Frequency (MHz)
Minimum
125
62.5
31.25
250
Maximum
350
175
87.5
700
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
28 Lead SOIC
28 Lead PLCC
Storage Temperature, T
STG
Rating
4.6V
0V to V
CC
-0.5V to V
CC
+ 0.5V
50mA
100mA
57C/W (0 mps)
45.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
160
16
Units
V
V
V
mA
mA
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER
5
Rev A 5/26/16
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
