CD4046BMS
December 1992
CMOS Micropower Phase Locked Loop
Description
CD4046BMS CMOS Micropower Phase-Locked Loop (PLL)
consists of a low power linear voltage-controlled oscillator (VCO)
and two different phase comparators having a common signal-
input amplifier and a common comparator input. A 5.2V zener
diode is provided for supply regulation if necessary.
The CD4046BMS is supplied in these 16-lead outline packages:
Braze Seal DIP H4W
Frit Seal DIP
H1F
Ceramic Flatpack H6W
VCO Section
The VCO requires one external capacitor C1 and one or two
external resistors (R1 or R1 and R2). Resistor R1 and capacitor
C1 determine the frequency range of the VCO and resistor R2
enables the VCO to have a frequency offset if required. The high
input impedance (10
12Ω
) of the VCO simplifies the design of low
pass filters by permitting the designer a wide choice of resistor-
to-capacitor ratios. In order not to load the low-pass filter, a
source-follower output of the VCO input voltage is provided at ter-
minal 10 (DEMODULATED OUTPUT). If this terminal is used, a
load resistor (RS) of 10kΩ or more should be connected from
this terminal to VSS. If unused this terminal should be left open.
The VCO can be connected either directly or through frequency
dividers to the comparator input of the phase comparators. A full
CMOS logic swing is available at the output of the VCO and
allows direct coupling to CMOS frequency dividers such as the
Intersil CD4024, CD4018, CD4020, CD4029, and CD4050. One
or more CD4018 (Preset Table Divide-By-N Counter) or CD4029
(Presettable Up/Down Counter) or CD4029 (Presettable Divide-
by-N Counter) or CD4029 (Presettable Up/Down Counter), or
CD4059A (Programmable Divide-by “N” Counter), together with
the CD4046BMS (Phase-Locked Loop) can be used to build a
micropower low-frequency synthesizer. A logic 0 on the INHIBIT
input “enables” the VCO and the source follower, while a logic 1
“turns off” both to minimize stand-by power consumption.
Features
• Very Low Power Consumption:
70µW (typ.) at VCO fo = 10kHz, VDD = 5V
• Operating Frequency Range Up to 1.4 MHz (typ.) at
VDD = 10V, RI = 5kΩ
• Low Frequency Drift: 0.04%/
o
C (typ.) at VDD = 10V
• Choice of Two Phase Comparators:
- Exclusive-OR Network (I)
- Edge-Controlled Memory Network with Phase-Pulse
Output for Lock Indication (II)
• High VCO Linearity: <1% (typ.) at VDD = 10V
• VCO Inhibit Control for ON-OFF Keying and Ultra-Low
Standby Power Consumption
• Source-Follower
(Demod. Output)
Output
of
VCO
Control
Input
• Zener Diode to Assist Supply Regulation
• Standardize, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
• FM Demodulator and Modulator
• Frequency Synthesis and Multiplication
• Frequency Discriminator
• Data Synchronization
• Voltage-to-Frequency Conversion
• Tone Decoding
• FSK - Modems
• Signal Conditioning
Pinout
CD4046BMS
TOP VIEW
PHASE PULSES 1
PHASE COMP I OUT 2
COMPARATOR IN 3
VCO OUT 4
INHIBIT 5
CI(1) 6
C1 (2) 7
VSS 8
16 VDD
15 ZENER
14 SIGNAL IN
13 PHASE COMP II OUT
12 R2 TO VSS
11 R1 TO VSS
10 DEMODULATOR OUT
9 VCO IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3312
7-886
CD4046BMS
Phase Comparators
SIGNAL INPUT (TERM. 14)
The phase-comparator signal input (terminal 14) can be
direct-coupled provided the signal swing is within CMOS
logic levels (logic “0”
≤30%
(VDD-VSS). logic “1”
≥70%
(VDD
- VSS)]. For smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal input.
Phase-comparator I is an exclusive -OR network; it operates
analogously to an overdriven balanced mixer. To maximize
the lock range, the signal and comparator-input frequencies
must have a 50% duty cycle. With no signal or noise on the
signal input, this phase comparator has an average output
voltage equal to VDD/2. The low-pass filter connected to the
output of phase-comparator I supplies the averaged voltage
to the VCO input, and causes the VCO to oscillate at the
center frequency (f
o
).
The frequency range of input signals on which the PLL will
lock if it was initially out of lock is defined as the frequency
capture range (2fc).
The frequency range of input signals on which the loop will
stay locked if it was initially in lock is defined as the fre-
quency lock range (2fL). The capture range is
≤
the lock
range.
With phase-comparator I the range of frequencies over
which the PLL can acquire lock (capture range) is dependent
on the low-pass-filter characteristics, and can be made as
large as the lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts of noise in
the input signal.
One characteristic of this type of phase comparator is that it
may lock onto input frequencies that are close to harmonics of
the VCO center-frequency. A second characteristic is that the
phase angle between the signal and the comparator input var-
ies between 0
o
and 180
o
, and is 90
o
at the center frequency.
Figure 1 shows the typical, triangular, phase-to-output
response characteristic of phase comparator I. Typical wave-
forms for a CMOS phase-locked-loop employing phase com-
parator I in locked condition of f
o
is shown in Figure 2.
AVERAGE OUTPUT
VOLTAGE
VDD
VCO OUTPUT (TERM 4) =
COMPARATOR INPUT (TERM 3)
PHASE COMPARATOR I
OUTPUT (TERM 2)
VCO INPUT (TERM 9) =
= LOW-PASS FILTER OUTPUT
VDD
VSS
FIGURE 2. TYPICAL WAVEFORMS FOR CMOS PHASE-
LOCKED LOOP EMPLOYING PHASE COMPARA-
TOR IN LOCKED CONDITION OF f
o
.
VDD/2
0
90
o
180
o
SIGNAL-TO-COMPARATOR
INPUTS PHASE DIFFERENCE
FIGURE 1. PHASE-COMPARATOR I CHARACTERISTICS AT
LOW-PASS FILTER OUTPUT
Phase comparator II is an edge-controlled digital memory
network. It consists of four flip-flop stages, control gating,
and a three-state output circuit comprising p- and n- type
drivers having a common output node. When the p-MOS or
n-MOS drivers are ON they pull the output up to VDD or
down to VSS, respectively. This type of phase comparator
acts only on the positive edges of the signal and comparator
inputs. The duty cycles of the signal and comparator inputs
are not important since positive transitions control the PLL
system utilizing this type of comparator. If the signal-input
frequency is higher than the comparator-input frequency, the
p-type output driver is maintained ON most of the time, and
both the n and p drivers OFF (3state) the remainder of the
time. If the signal-input frequency is lower than the compara-
tor-input frequency, the n-type output driver is maintained
ON most of the time, and both the n and p drivers OFF (3
state) the remainder of the time. If the signal and comparator
input frequencies are the same, but the signal input lags the
comparator input in phase, the n-type output driver is main-
tained ON for a time corresponding to the phase differences.
If the signal and comparator-input frequencies are the same,
but the comparator input lags the signal in phase, the p-type
output driver is maintained ON for a time corresponding to
the phase difference. Subsequently, the capacitor voltage of
the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in
both phase and frequency. At this stable point both p- and n-
type output drivers remain OFF and thus the phase compar-
ator output becomes an open circuit and holds the voltage
on the capacitor of the low-pass filter constant. Moreover the
signal at the “phase pulses” output is a high level which can
be used for indicating a locked condition. Thus, for phase
comparator II, no phase difference exists between signal and
comparator input over the full VCO frequency range. More-
over, the power dissipation due to the low-pass filter is
reduced when this type of phase comparator is used
because both the p- and n-type output drivers are OFF for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range, independent of the low-pass filter. With
no signal present at the signal input, the VCO is adjusted to
its lowest frequency for phase comparator II. Figure 15
shows typical waveforms for a CMOS PLL employing phase
comparator II in a locked condition.
AVERAGE OUTPUT VOLTAGE (V)
7-887
Specifications CD4046BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
Ceramic DIP and FRIT Package . . . . . 80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
3 State Leakage
Current
VIL
VIH
VIL
VIH
IOZL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIN = VDD or GND
VOUT = 0V
VDD = 20V
VDD = 18V
3 State Leakage
Current
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VDD = 18V
3
1
2
3
1
2
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
+25
o
C,
LIMITS
TEMPERATURE
+25
o
C
+125
o
C
-55
o
C
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
MIN
-
-
-
-100
-1000
-100
-
-
-
-
14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
+25
o
C
+125 C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+125
o
C,
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25 C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
o
o
-55
o
C
VOH > VOL <
VDD/2 VDD/2
-
3.5
-
11
-100
-1000
-100
-
-
-
1.5
-
4
-
-
-
-
100
1000
100
V
V
V
V
nA
nA
nA
nA
nA
nA
7-888
Specifications CD4046BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
GROUP A
SUBGROUPS
1
3
1
3
LIMITS
TEMPERATURE
+25
o
C
-55
o
C
+25
o
C
-55
o
C
MIN
-
-
-
-
MAX
4
4
160
160
UNITS
mA
mA
µA
µA
PARAMETER
Quiescent Leakage
Phase Comparator
(Bias Amp Leakage)
SYMBOL
CONDITIONS
(NOTE 1)
BIAS LKG VDD = 20V, VIN = VDD or GND
PIN 14 Open
Pin 5 = VDD
VDD = 20V, VIN = VDD or GND
PIN 14 = VSS or VDD
Pin 5 = VDD
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
+25
o
C
LIMITS
MIN
-
MAX
360
UNITS
mV
PARAMETER
AC Coupled Signal Input
Voltage Sensitivity
(Peak to Peak)
NOTES:
SYMBOL
VS
CONDITIONS
(NOTE 1)
VDD = 5V, Input Frequency =
100kHz Sine Wave
1. Go/No Go test with limits applied to inputs.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
SYMBOL
VOL
VOL
VOH
VOH
IOL5
CONDITIONS
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current
(Source)
Output Current
(Source)
Output Current
(Source)
Output Current
(Source)
Input Voltage Low
Input Voltage High
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55 C
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-55
o
C
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
VIL
VIH
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
o
MIN
-
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
-
-
-
-
-
-
-
+7
MAX
50
50
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
-
UNITS
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
7-889
Specifications CD4046BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Quiescent Leakage
Phase Comparator
(Bias Amp Leakage)
SYMBOL
BIAS LKG VDD = 5
VIN =
VDD or
GND
CONDITIONS
Pin 14 Open
Pin 5 = VDD
Pin 14 = VSS or VDD
Pin 5 = VDD
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
+25
o
C/-55
o
C
+25
o
C/-55
o
C
+25
o
C/-55
o
C
+25
o
C/-55
o
C
+25
o
C/-55
o
C
+25
o
C/-55
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
-
-
-
-
MAX
0.2
20
1.0
40
1.5
80
660
1800
UNITS
mA
µA
mA
µA
mA
µA
mV
mV
VDD = 10 Pin 14 Open
VIN =
Pin 5 = VDD
VDD or
Pin 14 = VSS or VDD
GND
Pin 5 = VDD
VDD = 15 Pin 14 Open
VIN =
Pin 5 = VDD
VDD or
Pin 14 = VSS or VDD
GND
Pin 5 = VDD
AC Coupled Signal In-
put Voltage Sensitivity
(Peak to Peak)
VS
VDD = 10V, Input Frequency =
100kHz Sine Wave
VDD = 15V, Input Frequency =
100kHz Sine Wave
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
AC Coupled Signal Input
Voltage Sensitivity
VS
VDD = 5V
Input Frequency = 100kHz
Sine Wave
1, 2, 3
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
µA
V
V
V
V
V
mV
NOTES: 1. All voltages referenced to device GND.
2. Go/No Go test with limits applied to inputs.
3. See Table 2 for +25
o
C limit.
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
±
1.0µA
±
20% x Pre-Test Reading
±
20% x Pre-Test Reading
DELTA LIMIT
7-890
嵌入式系统
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