assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCE INFORMATION
06/12/02
Rev. 00A
1
IS61LSSD102418
CLOCKING AND ADDRESSING SCHEMES
A
Σ
2x2B4 SigmaQuad is a synchronous device. It
employs two input register clock inputs, K and
K.
K
and
K
are independent single ended clock inputs, not
differential inputs to a single differential clock input
buffer.
The device also allows the user to manipulate the
output register clock inputs quasi independently with
the C and
C
clock inputs. C and
C
are also indepen-
dent single ended clock inputs, not differ ential inputs.
If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead. Each
ISSI
CQ and
CQ,
that are synchronized with read data
output. When used in a Source Synchronous clocking
scheme these Echo Clock outputs can be used to fire
input registers at the data’s destination.
Because Separate I/O
Σ
2x2B4 RAMs always transfer
data in two packets, A0 is internally set to 0 for the
first read or write transfer, and automatically
incremented by 1 for the next transfer. Since the LSB
is tied off internally, the address field of a
Σ
2x2B4
RAM is always two address pin less than the adver-
tised index depth (e.g., the 1M x 18 has a 256K ad-
dressable index).
®
Σ
2x2B4 SigmaRAM also supplies Echo Clock outputs,
1M x 18 SIGMAQUAD SRAM
1
2
3
TOP VIEW
4
5
6
7
8
9
10
11
A
B
C
D
E
F
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MCL/SA
(144Mb)
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
NC/SA
(36Mb)
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Vss
V
SS
SA
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
Vss
SA
SA
SA
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
NC
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
Vss
SA
SA
SA
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Vss
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
MCL/SA
(72Mb)
NC
Q7
NC
D6
NC
NC
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
G
H
J
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
K
L
M
N
P
R
NC
NC
SA
TDO
TCK
11 x 15 Bump BGA
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2.
BW0
controls writes to D0:D8.
BW1
controls writes to D9:D17.
3. MCL = Must Connect Low
4. It is recommended that H1 be tied low for compatibility with future devices.
SA
SA
13 x 15 mm2 Body
1 mm Bump Pitch
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCE INFORMATION
Rev. 00A
06/12/02
IS61LSSD102418
PIN DESCRIPTION TABLE
Symbol
SA
Pin Location
B4, B8, C5, C7, N5, N6,
N7, P4, P5, P7, P8, R3,
R4, R5, R7, R8, R9
A9
A8
A4
B7, A5
A7, B5
B6
A6
P6
R6
R10
R11
R2
R1
H2, H10
H11
A2, A10
A11
A1
B3, C3, C11, D2, D11, E10
F3, G2, G11, J3, J11, K10, L3
M3, M11, N2, N11, P10
B2, B11, C10, D3, E3, E11, F2
F11, G3, J10, K3, K11, L2, L11
M10, N3, P3, P11
B1, B9, B10, C1, C2, C9, D1
D9, D10, E1, E2, E9, F1, F9
F10, G1, G9, G10, J1, J2
J9, K1, K2, K9, L1, L9, L10, M1
M2, M9, N1, N9, N10, P1, P2, P9
NC
V
DD
V
DDQ
A3, C6, H1
F5, F7, G5, G7, H5, H7, J5, J7,
K5, K7
No Connect
Power Supply
—
Supply
Supply
Description
Address
Type
Input
ISSI
Comments
—
®
SA
R
W
BW0
-
BW1
NC
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
MCL
CQ
CQ
D0 - D17
Address
Read
Writes
Byte Writes
No Connect
Input Clock
Input Clock
Output Clock
Output Clock
Test mode Select
Test data Input
Test Clock Input
Test Data Output
HSTK InputReference Voltage
Output Impedance matching Input
Must Connect Low
Echo Clock Output
Echo Clock-bar Output
Data Inputs
Input
Input
Input
Input
—
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Output
Output
Input
—
Active Low
Active Low
Active Low
—
Active High
Active Low
Active High
Activ Low
—
—
—
—
—
—
—
Echoes C or K Clock
Echoes
C
or
K
Clock
—
Q0 - Q17
Data Output
Output
—
NC
No Connect
—
—
—
1.8 V Nominal
1.5 V Nominal
E4, E8, F4, F8, G4, G8, Output Buffer Supply
H3, H4, H8, H9, J4, J8, K4,
K8, L4, L8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCE INFORMATION
06/12/02
Rev. 00A
3
IS61LSSD102418
PIN DESCRIPTION TABLE
Symbol
V
SS
Pin Location
C4, C8, D4, D5, D6, D7, D8, E5
E6, E7, F6, G6, H6, J6, K6, L5, L6
L7, M4, M5, M6, M7, M8, N4, N8
Note:
NC = Not Connected to die or any other pin
ISSI
Description
Ground
Type
Output
Comments
—
®
BACKGROUND
Separate I/O SigmaRAMs have been designed to be
closely related to Common I/O SigmaRAMs in pinout
and overall architecture. The similarities give Separate
I/O SigmaRAMs a cost advantage by allowing users
and vendors to reuse supporting infrastructure and
design elements. Separate I/O SigmaRAMs come in
Single and two Double Data Rate configurations.
Because they are designed to operate with both the
input data pins and the output data pins operating at
full speed all the time, Separate I/O SigmaRAMs
produce twice the bandwidth of Common I/O SRAMs
of the same speed and output bus width. But because
the bandwidth of a memory device is set by the
architecture and performance of the core array, the
bandwidth available from each port of a Separate I/O
SRAM is half the bandwidth available from the single
port of an otherwise equivalent Common I/O SRAM.
Separate I/O SRAMs, from a system architecture point
of view, are attractive in applications where alternating
reads and writes are needed. Therefore, the
SigmaRAM Separate I/O interface and truth table are
optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple
reads or multiple writes are needed because burst read
or write transfers from Separate I/O SRAMs cut the
RAM’s bandwidth in half.
determined by the internal performance of the RAM and
they are all based on the same internal circuits. Differ-
ences between the truth tables of the different Separate
I/O SigmaRAMs, or any other Separate I/O SRAMs,
follow from differences in how the RAM’s interface is
contrived to interact with the rest of the system. Each
mode of operation has it’s own advantages and disad-
vantages. The user should consider the nature of the
work to be done by the RAM to evaluate which version
is best suited to the application at hand.
A Separate I/O SigmaRAM can begin an alternating
sequence of reads and writes with either a read or a
write. In order for any separate I/O SRAM that shares a
common address between it’s two ports to keep both
ports running all the time, the RAM must implement
some sort of burst transfer protocol. The burst must be
at least long enough to cover the time the opposite port
is receiving instructions on what to do next. The rate at
which a RAM can accept a new random address is the
most fundamental performance metric for the RAM.
Each of the three Separate I/O SigmaRAMs support the
same address rate because random address rate is
4
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCE INFORMATION
Rev. 00A
06/12/02
IS61LSSD102418
Although the Separate I/O SigmaRAM family of pinouts
has been designed to support Single and Double Data
Rate options, not all SigmaRAM implementations will
support both protocols. This particular data sheet
covers the Double Data Rate Burst of 4 (Σ2x2B4)
Separate I/O SigmaRAM
ISSI
®
The character of the applications for fast synchronous
SRAMs in networking systems are extremely diverse.
SigmaRAMs ha been developed to address the diverse
needs of the networking market in a manner that can
be supported with a unifie development and manufac-
turing infrastructure. SigmaRAMs address each of the
bus protocol options commonly found in networking
systems.
ALTERNATING READ-WRITE OPERA-
TIONS
Separate I/O SigmaRAMs follow a few simple rules of
operation.
- Read or Write commands issued on one port are
never allowed to interrupt a operation in progress on
the other port.
- Read or Write data transfers in progress may not be
interrupted and re-started.
- A Read of a given address location immediately after
the location has just been written produces the just-
written data. (i.e. SigmaRAMs are “coherent”.)
-
R
and
W
high always deselects the RAM but does not
disable the CQ or
CQ
output pins.
- All address, data, and control inputs are sampled on
clock edges.
In order to enforce these rules, each RAM combines
present state information with command inputs. See
the Truth Table for details.
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