1-to-1 2.5V, 3.3V
Differential-to-LVCMOS/LVTTL Translator
830S21I-01
Datasheet
General Description
830S21I-01 is a 1-to-1 Differential-to- LVCMOS/ LVTTL translator
and a member of the family of High Performance Clock Solutions
from IDT. The differential input is highly flexible and can accept the
following input types: LVPECL, LVDS, LVHSTL, SSTL and HCSL.
The small 8-lead SOIC footprint makes this device ideal for use in
applications with limited board space.
Features
•
•
•
•
•
•
•
•
•
•
One LVCMOS/LVTTL output
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz
Part-to-part skew: 525ps (maximum)
Additive phase jitter, RMS: 0.11ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V and 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK Pullup/Pulldown
Q
nCLK Pullup/Pulldown
OE
Pullup
Pin Assignment
nc
CLK
nCLK
OE
1
2
3
4
8
7
6
5
V
DD
Q
nc
GND
830S21I-01
8-Lead SOIC
3.9mm x 4.9mm x 1.375mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
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December 10, 2015
830S21I-01 Datasheet
Table 1. Pin Descriptions
Number
1, 6
2
3
4
5
7
8
Name
nc
CLK
nCLK
OE
GND
Q
V
DD
Unused
Input
Input
Input
Power
Output
Power
Pullup/
Pulldown
Pullup/
Pulldown
Pullup
Type
Description
No connect.
Non-inverting differential clock input.
Inverting differential clock input.
Output enable pin. See Table 3. LVCMOS / LVTTL interface levels.
Power supply ground.
Single-ended clock output. LVCMOS / LVTTL interface levels.
Positive supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
V
DD
= 3.465V
V
DD
= 2.625V
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
Test Conditions
Minimum
Typical
4
51
51
10
8
10
12
Maximum
Units
pF
k
k
pF
pF
R
OUT
Function Tables
Table 3. OE Configuration Table
Input
OE
0
1 (default)
Operation
Output Q is in a high-impedance state.
Output Q is enabled.
©2015 Integrated Device Technology, Inc
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December 10, 2015
830S21I-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
93.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
12
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
11
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V or 2.5V
-150
2.6
1.8
0.5
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
10
Units
V
V
V
V
µA
µA
V
V
V
V
IL
I
IH
I
IL
V
OH
V
OL
NOTE 1: Outputs terminated with 50 to V
DD
/2. See Parameter Measurement Information,
Output Load Test Circuit diagrams.
©2015 Integrated Device Technology, Inc
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830S21I-01 Datasheet
Table 4D. Differential DC Characteristics,
V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
0.15
GND + 0.5
1.5
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(pp)
tjit
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay, NOTE 1
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
350MHz, Integration Range
(12kHz – 20MHz)
20% to 80%
ƒ
266MHz
85
47
0.11
500
53
8
8
0.95
Test Conditions
Minimum
Typical
350
1.95
525
Maximum
Units
MHz
ns
ps
ps
ps
%
ns
ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V
DD
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
Table 5B. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(pp)
tjit
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay, NOTE 1
Part-to-Part Skew; NOTE 2, 3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
350MHz, Integration Range
(12kHz – 20MHz)
20% to 80%
ƒ
266MHz
125
47
0.11
500
53
8
8
1
Test Conditions
Minimum
Typical
350
2
550
Maximum
Units
MHz
ns
ps
ps
ps
%
ns
ns
For NOTES, see Table 5A above.
©2015 Integrated Device Technology, Inc
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December 10, 2015
830S21I-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 350MHz
12kHz to 20MHz = 0.11ps (typical)
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
©2015 Integrated Device Technology, Inc
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December 10, 2015
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