PowerPC 403GC
32-Bit RISC
Embedded Controller
Features
•
PowerPC
™
RISC CPU and instruction set
architecture
•
Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
•
Separate instruction cache and write-back
data cache, both two-way set-associative
•
Memory management unit
–64-entry, fully associative TLB array
–Variable page size (1KB-16MB)
–Flexible TLB management
•
Individually programmable on-chip
controllers for:
–Four DMA channels
–DRAM, SRAM, and ROM banks
–External interrupts
•
Flexible interface to external bus masters
Data
Sheet
Overview
The PowerPC 403GC 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GC RISC CPU executes at sustained speeds
approaching one cycle per instruction. On-chip
caches and integrated DRAM and SRAM control
functions reduce chip count and design
complexity in systems, while improving system
throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GC bus
interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a
maximum of four DRAM banks, can be
configured individually, allowing the BIU to
manage devices or memory banks with differing
control, timing, or bus width requirements.
•
Hardware multiplier and divider
•
Thirty-two 32-bit general purpose registers
Applications
•
Set-top boxes
•
Consumer electronics and video games
•
Telecommunications and networking
•
Office automation (printers, copiers, fax)
•
Personal digital assistants (PDA)
Specifications
•
25MHz, 33MHz, and 40MHz versions
•
Interfaces to both 3V and 5V technologies
•
Low-power 3.3V operation with built-in
power management and stand-by mode
•
Low-cost 160 lead PQFP package
•
0.5
µ
m triple-level-metal CMOS
Interrupt
Controller
JTAG
Port
Serial
Port
4-Channel
DMA
Controller
(Address
and
Control)
Timers
RISC Execution Unit
Memory Management Unit
Instruction
Cache Unit
Data
Cache Unit
On-chip
Peripheral
Bus
Bus Interface Unit
DRAM Controller
I/O Controller
Data Address
Bus Bus
DRAM
Controls
SRAM, ROM, I/O
Controls
IBM PowerPC 403GC
The 403GC RISC controller consists of a
pipelined RISC processor core and several
peripheral interface units: BIU, DMA controller,
asynchronous interrupt controller, serial port, and
JTAG debug port.
The RISC processor core includes the internal
2KB instruction cache and 1KB data cache,
reducing overhead for data transfers to or from
external memory. The instruction queue logic
manages branch prediction, folding of branch
and condition register logical instructions, and
instruction prefetching to minimize pipeline
stalls.The integrated memory management unit
provides robust memory management and
protection functions, optimized for embedded
environments.
When noncacheable operands are being
transferred, data can pass directly between the
EXU and the BIU, which interfaces to the external
memory being accessed.
Special Purpose Registers
Special purpose registers are used to control
debug facilities, timers, interrupts, the protection
mechanism, memory cacheability, and other
architected processor resources. SPRs are
accessed using move to/from special purpose
register (mtspr/mfspr) instructions, which move
operands between GPRs and SPRs.
Supervisory programs can write the appropriate
SPRs to configure the operating and interface
modes of the execution unit. The condition
register (CR) and machine state register (MSR)
are written by internal control logic with program
execution status and machine state, respectively.
Status of external interrupts is maintained in the
external interrupt status register (EXISR). Fixed-
point arithmetic exception status is available from
the exception register (XER).
RISC CPU
The RISC core comprises four tightly coupled
functional units: the execution unit (EXU), the
memory management unit (MMU), the data
cache unit (DCU), and the instruction cache unit
(ICU). Each cache unit consists of a data array,
tag array, and control logic for cache
management and addressing. The execution unit
consists of general purpose registers (GPR),
special purpose registers (SPR), ALU, multiplier,
divider, barrel shifter, and the control logic
required to manage data flow and instruction
execution within the EXU.
The EXU handles instruction decoding and
execution, queue management, branch
prediction, and branch folding. The instruction
cache unit passes instructions to the queue in the
EXU or, in the event of a cache miss, requests a
fetch from external memory through the bus
interface unit. The MMU provides translation and
memory protection for instruction and data
accesses, using a unified 64-entry, fully
associative TLB array.
Device Control Registers
Device control registers (DCR) are used to
manage I/O interfaces, DMA channels, SRAM
and DRAM memory configurations and timing,
and status/address information regarding bus
errors. DCRs are accessed using move to/from
device control register (mtdcr/mfdcr) instructions,
which move operands between GPRs and DCRs.
Instruction Set
Table 1 summarizes the 403GC instruction set by
categories of operations. Most instructions
execute in a single cycle, with the exceptions of
load/store multiple, load/store string, multiply, and
divide instructions.
Bus Interface Unit
The bus interface unit integrates the functional
controls for data transfers and address
operations other than those which the DMA
controller handles. DMA transfers use the
address logic in the BIU to output the memory
addresses being accessed.
General Purpose Registers
Data transfers to and from the EXU are handled
through the bank of 32 GPRs, each 32 bits wide.
Load and store instructions move data operands
between the GPRs and the data cache unit,
except in the cases of noncacheable data or
cache misses. In such cases the DCU passes
the address for the data read or write to the BIU.
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IBM PowerPC 403GC
Control functions for direct-connect I/O devices
and for DRAM, SRAM, or ROM banks are
provided by the BIU. Burst access for SRAM,
ROM, and page-mode DRAM devices is
supported for cache fill and flush operations.
The BIU controls the transfer of data between the
external bus and the instruction cache, the data
cache, or registers internal to the processor core.
The BIU also arbitrates among external bus
master and DMA transfers, the internal buses to
the cache units and the register banks, and the
serial port on the on-chip peripheral bus (OPB).
bank size, bank location, number of wait states,
and timings of chip selects, byte enables, and
output enables are all user-programmable.
Memory Management Unit
The memory management unit (MMU) supports
address translation and protection functions for
embedded applications. When used with
appropriate system level software, the MMU
provides the following functions: translation of
4GB logical address space into physical
addresses, independent enabling of instruction
and data translation/protection, page level
cacheability and access control via the
translation mechanism, software control of page
replacement strategy, and additional control over
protection via zones.
The fully associative 64-entry TLB array handles
both instruction and data accesses. The
translation for any virtual address can be placed
in any one of the 64 entries, allowing maximum
flexibility by TLB management software. Each
TLB entry contains a translation for a page that
can be any one of eight sizes from 1KB to 16MB,
incrementing by powers of 4.
The TLB can simultaneously contain any mix of
page sizes. This feature enables the use of small
pages when maximum granularity is required,
reducing the amount of wasted memory when
compared to the more common fixed 4KB page
size.
Memory Addressing Regions
The 403GC can address an effective range of
four gigabytes, mapped to 3.5GB (256MB for
SRAM/ROM or other I/O, 256MB DRAM, and
3GB OPB/reserved) of physical address space
containing twenty-eight 128MB regions.
Cacheability with respect to the instruction or
data cache is programmed via the instruction and
data cache control registers, respectively.
Within the DRAM and SRAM/ROM regions, a
total of eight banks of devices are supported.
Each bank can be configured for 8-, 16-, or 32-bit
devices.
For individual DRAM banks, the number of wait
states, bank size,
RAS
-to-
CAS
timing, use of an
external address multiplexer (for external bus
masters), and refresh rate are user-
programmable. For each SRAM/ROM bank, the
Table 1. 403GC Instructions by Category
Category
Data Movement
Arithmetic / Logical
Comparison
Branch
Condition
Rotate/Shift
Cache Control
Interrupt Control
Processor Management
load, store
add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign
extension, count leading zeros
compare, compare logical, compare immediate
branch, branch conditional
condition register logical
rotate, rotate and mask, shift left, shift right
invalidate, touch, zero, flush, store
write to external interrupt enable bit, move to/from machine state register,
return from interrupt, return from critical interrupt
system call, synchronize, move to/from device control registers, move to/
from special purpose registers
Base Instructions
3
IBM PowerPC 403GC
Instruction Cache Unit
The instruction cache unit (ICU) is a two-way set-
associative 2KB cache memory unit with
enhancements to support branch prediction and
folding. The ICU is organized as 64 sets of 2
lines, each line containing 16 bytes. A separate
bypass path is available to handle cache-
inhibited instructions and to improve performance
during line fill operations.
The cache can send two cached instructions per
cycle to the execution unit, allowing instructions
to be folded out of the queue without interrupting
normal instruction flow. When a branch
instruction is folded and executed in parallel with
another instruction, the ICU provides two more
instructions to replace both of the instructions
just executed so that bandwidth is balanced
between the ICU and the execution unit.
the block and then wrapping around to fill the
remaining fullwords at the beginning of the block.
DMA Controller
The four-channel DMA controller manages block
data transfers in buffered, fly-by and memory-to-
memory transfer modes with options for burst-
mode operation. In fly-by and buffered modes,
the DMA controller supports transactions
between memory and peripheral devices.
Each DMA channel provides a control register, a
source address register, a destination address
register, a transfer count register, and a chained
count register. Peripheral set-up cycles, wait
cycles, and hold cycles can be programmed into
each DMA channel control register. Each
channel supports chaining operations. The DMA
status register holds the status of all four
channels.
Data Cache Unit
The data cache unit is provided to minimize the
access time of frequently used data items in main
store. The 1KB cache is organized as a two-way
set associative cache. There are 32 sets of 2
lines, each line containing 16 bytes of data. The
cache features byte-writeability to improve the
performance of byte and halfword store
operations.
Cache operations are performed using a write-
back strategy. A write-back cache only updates
locations in main storage that corresponds to
changed locations in the cache. Data is flushed
from the cache to main storage whenever
changed data needs to be removed from the
cache to make room for other data.
The data cache may be disabled for a 128MB
memory region via control bits in the data cache
control register or on a per-page basis if the
MMU is enabled for data translation. A separate
bypass path is available to handle cache-
inhibited data operations and to improve
performance during line fill operations.
Cache flushing and filling are triggered by load,
store, and cache control instructions executed by
the processor. Cache blocks are loaded starting
at the requested fullword, continuing to the end of
Exception Handling
Table 2 summarizes the 403GC exception
priorities, types, and classes. Exceptions are
generated by interrupts from internal and
external peripherals, instructions, the internal
timer facility, debug events or error conditions.
Six external interrupt signals are provided on the
403GC: one critical and five general-purpose, all
individually maskable.
All exceptions fall into three basic classes:
asynchronous imprecise exceptions,
synchronous precise exceptions, and
asynchronous precise exceptions. Asynchronous
exceptions are caused by events external to
processor execution, while synchronous
exceptions are caused by instructions.
Except for a system reset or machine check, all
403GC exceptions are handled precisely. Precise
handling implies that the address of the
excepting instruction (synchronous exceptions
other than system call) or the address of the next
sequential instruction (asynchronous exceptions
and system call) is passed to the exception
handling routine. Precise handling also implies
that all instructions prior to the excepting
instruction have completed execution and have
written back their results.
4
IBM PowerPC 403GC
Asynchronous imprecise exceptions include
system resets and machine checks.
Synchronous precise exceptions include most
debug exceptions, program exceptions, data
storage violations, TLB misses, system calls, and
alignment error exceptions. Asynchronous
precise exceptions include the critical interrupt
exception, external interrupts, and internal timer
facility exceptions and some debug events.
Only one exception is handled at a time. If
multiple exceptions occur simultaneously, they
are handled in priority order.
The 403GC processes exceptions as reset,
critical, or noncritical. Four exceptions are
defined as critical: machine check exceptions,
debug exceptions, exceptions caused by an
active level on the critical interrupt pin, and the
first time-out from the watchdog timer.
When a noncritical exception is taken, special
purpose register Save/Restore 0 (SRR0) is
loaded with the address of the excepting
instruction (synchronous exceptions other than
system call) or the next sequential instruction to
be processed (asynchronous exceptions and
system call). If the 403GC is executing a
multicycle instruction (load/store multiple, load/
store string, multiply or divide), the instruction is
terminated and its address stored in SRR0.
Save/Restore Register 1 (SRR1) is loaded with
the contents of the machine state register. The
MSR is then updated to reflect the new context of
the machine. The new MSR contents take effect
beginning with the first instruction of the
exception handling routine.
At the end of the exception handling routine,
execution of a return from interrupt (rfi)
instruction forces the contents of SRR0 and
SRR1 to be loaded into the program counter and
the MSR, respectively. Execution then begins at
the address in the program counter.
The four critical exceptions are processed in a
similar manner. When a critical exception is
taken, SRR2 and SRR3 hold the next sequential
address to be processed when returning from the
exception and the contents of the machine state
register, respectively. After the critical exception
handling routine, return from critical interrupt
(rfci) forces the contents of SRR2 and SRR3 to
be loaded into the program counter and the
MSR, respectively.
Timers
The 403GC contains four timer functions: a time
base, a programmable interval timer (PIT), a
fixed interval timer (FIT), and a watchdog timer.
The time base is a 64-bit counter incremented at
the timer clock rate. The timer clock may be
driven by either an internal signal equal to the
processor clock rate or by a separate external
timer clock pin. No interrupts are generated when
the time base rolls over.
Table 2. 403GC Exception Priorities, Types and Classes
Priority
1
2
3
4
5
6
7
8
9
10
Exception Type
System Reset
Machine Check
Debug
Critical Interrupt
WatchdogTimer Time-out
Exception Class
Asynchronous imprecise
Asynchronous imprecise
Synchronous precise
(except UDE and EXC)
Asynchronous precise
Asynchronous precise
Program Exception, Data Storage Exception,TLB Miss, and Synchronous precise
System Calls
Alignment Exceptions
External Interrupts
Fixed Interval Timer
Programmable Interval Timer
Synchronous precise
Asynchronous precise
Asynchronous precise
Asynchronous precise
5
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