HIP6012
TM
Data Sheet
April 2001
File Number
4324.1
Buck and Synchronous-Rectifier
Pulse-Width Modulator (PWM) Controller
The HIP6012 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6012 integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.
The output voltage of the converter can be precisely
regulated to as low as 1.27V, with a maximum tolerance of
±1.5%
over temperature and line voltage variations.
The HIP6012 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.
The HIP6012 protects against overcurrent conditions by
inhibiting PWM operation. The HIP6012 monitors the current
by using the r
DS(ON)
of the upper MOSFET which eliminates
the need for a current sensing resistor.
Features
• Drives Two N-Channel MOSFETs
• Operates From +5V or +12V Input
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio
• Excellent Output Voltage Regulation
- 1.27V Internal Reference
-
±1.5%
Over Line Voltage and Temperature
• Overcurrent Fault Monitor
- Does Not Require Extra Current Sensing Element
- Uses MOSFETs r
DS(ON)
• Small Converter Size
- Constant Frequency Operation
- 200kHz Free-Running Oscillator Programmable from
50kHz to Over 1MHz
• 14 Pin, SOIC and TSSOP Packages
Applications
• Power Supply for Pentium®, Pentium Pro, PowerPC™ and
Alpha™ Microprocessors
• High-Power 5V to 3.xV DC-DC Regulators
• Low-Voltage Distributed Power Supplies
Pinout
HIP6012
(SOIC, TSSOP)
TOP VIEW
RT
OCSET
SS
COMP
FB
EN
GND
1
2
3
4
5
6
7
14 VCC
13 PVCC
12 LGATE
11 PGND
10 BOOT
9
8
UGATE
PHASE
Ordering Information
PART
NUMBER
HIP6012CB
HIP6012CB-T
HIP6012CV
HIP6012CV-T
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
14 Ld SOIC
14 Ld SOIC Tape and Reel
14 Ld TSSOP
14 Ld TSSOP Tape and
Reel
PKG.
NO.
M14.15
M14.15
M14.173
M14.173
PowerPC™ is a trademark of IBM.
Alpha™ is a trademark of Digital Equipment Corporation.
Pentium® is a registered trademark of Intel Corporation.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
HIP6012
Typical Application
12V
VCC
OCSET
MONITOR AND
PROTECTION
EN
BOOT
RT
+5V OR +12V
SS
OSC
UGATE
PHASE
+V
O
PVCC
+
+12V
HIP6012
REF
-
LGATE
PGND
GND
FB
+
-
COMP
Block Diagram
VCC
POWER-ON
RESET (POR)
10µA
+
OCSET
EN
-
OVER-
CURRENT
4V
SOFT-
START
SS
BOOT
UGATE
PHASE
200µA
1.27 VREF
REFERENCE
+
PWM
COMPARATOR
-
+
INHIBIT
PWM
FB
COMP
ERROR
AMP
-
GATE
CONTROL
LOGIC
PVCC
LGATE
PGND
GND
RT
OSCILLATOR
2
HIP6012
Absolute Maximum Ratings
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V
Boot Voltage, V
BOOT
- V
PHASE
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.3V to V
CC
+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range. . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(Lead tips only)
Operating Conditions
Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V
±10%
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
r
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 fo details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
POWER-ON RESET
Rising V
CC
Threshold
Falling V
CC
Threshold
Enable - Input threshold Voltage
Rising V
OCSET
Threshold
OSCILLATOR
Free Running Frequency
Total Variation
Ramp Amplitude
REFERENCE
Reference Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
GATE DRIVERS
Upper Gate Source
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
PROTECTION
OCSET Current Source
Soft Start Current
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
EN = V
CC
; UGATE and LGATE Open
EN = 0V
-
-
5
50
-
100
mA
µA
V
OCSET
= 4.5VDC
V
OCSET
= 4.5VDC
V
OCSET
= 4.5VDC
-
8.8
0.8
-
-
-
-
1.27
10.4
-
2.0
-
V
V
V
V
R
T
= OPEN, V
CC
= 12
6kΩ < R
T
to GND < 200kΩ
∆V
OSC
R
T
= OPEN
180
-20
-
200
-
1.9
220
+20
-
kHz
%
V
P-P
1.251
1.270
1.289
V
-
GBW
SR
COMP = 10pF
-
-
88
15
6
-
-
-
dB
MHz
V/µs
I
UGATE
R
UGATE
I
LGATE
R
LGATE
V
BOOT
- V
PHASE
= 12V, V
UGATE
= 6V
I
LGATE
= 0.3A
V
CC
= 12V, V
LGATE
= 6V
I
LGATE
= 0.3A
350
-
300
-
500
5.5
450
3.5
-
10
-
6.5
mA
W
mA
W
I
OCSET
I
SS
V
OCSET
= 4.5VDC
170
-
200
10
230
-
µA
µA
3
HIP6012
Typical Performance Curves
80
70
60
C
GATE
= 3300pF
I
VCC
(mA)
50
40
30
20
10
0
100
C
GATE
= 10pF
C
GATE
= 1000pF
1000
RESISTANCE (kΩ)
R
T
PULLUP
TO +12V
100
R
T
PULLDOWN
TO V
SS
10
10
100
SWITCHING FREQUENCY (kHz)
1000
200
300
400
500
600
700
800
900
1000
SWITCHING FREQUENCY (kHz)
FIGURE 1. R
T
RESISTANCE vs FREQUENCY
FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY
Functional Pin Descriptions
An overcurrent trip cycles the soft-start function.
RT
OCSET
SS
COMP
FB
EN
GND
1
2
3
4
5
6
7
14 VCC
13 PVCC
12 LGATE
11 PGND
10 BOOT
9
8
UGATE
PHASE
SS (Pin 3)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft-
start interval of the converter.
COMP (Pin 4) and FB (Pin 5)
COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.
RT (Pin 1)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Fs
≈
200 kHz
+
5
•
10
------------------
R
T
6
EN (Pin 6)
This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft start pin is
discharged and the UGATE and LGATE pins are held low.
(R
T
to GND)
GND (Pin 7)
Signal ground for the IC. All voltage levels are measured with
respect to this pin.
Conversely, connecting a pull-up resistor (R
T
) from this pin to
V
CC
reduces the switching frequency according to the
following equation.:
4
•
10
Fs
≈
200kHz
– ------------------
R
T
7
PHASE (Pin 8)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for overcurrent protection. This pin also provides the return
path for the upper gate drive.
(R
T
to 12V)
OCSET (Pin 2)
Connect a resistor (R
OCSET
) from this pin to the drain of the
upper MOSFET. R
OCSET
, an internal 200µA current source
(I
OCS
), and the upper MOSFET on-resistance (r
DS(ON)
) set
the converter overcurrent (OC) trip point according to the
following equation:
I
OCS
•
R
OCSET
I
PEAK
= -------------------------------------------
-
r
DS
(
ON
)
UGATE (Pin 9)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 10)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
4
HIP6012
PGND (Pin 11)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 12)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
SOFT-START
(1V/DIV.)
PVCC (Pin 13)
Provide a bias supply for the lower gate drive to this pin.
VCC (Pin 14)
Provide a 12V bias supply for the chip to this pin.
0V
0V
t1
t2
OUTPUT
VOLTAGE
(1V/DIV.)
Functional Description
Initialization
The HIP6012 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
voltage (V
IN
) on the OCSET pin. The level on OCSET is
equal to V
IN
Less a fixed voltage drop (see overcurrent
protection). With the EN pin held to V
CC
, the POR function
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V
IN
and V
CC
are equivalent and the
+12V power source must exceed the rising V
CC
threshold
before POR initiates operation.
The Power-On Reset (POR) function inhibits operation with
the chip disabled (EN pin low). With both input supplies
above their POR thresholds, transitioning the EN pin high
initiates a soft start interval.
t3
TIME (5ms/DIV.)
FIGURE 3. SOFT-START INTERVAL
SOFT-START
OUTPUT INDUCTOR
4V
2V
0V
15A
10A
5A
0A
TIME (20ms/DIV.)
Soft Start
The POR function initiates the soft start sequence. An
internal 10µA current source charges an external capacitor
(C
SS
) on the SS pin to 4V. Soft start clamps the error
amplifier output (COMP pin) and reference input (+ terminal
of error amp) to the SS pin voltage. Figure 3 shows the soft
start interval with C
SS
= 0.1µF. Initially the clamp on the
error amplifier (COMP pin) controls the converter’s output
voltage. At t1 in Figure 3, the SS voltage reaches the valley
of the oscillator’s triangle wave. The oscillator’s triangular
waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width
that charge the output capacitor(s). This interval of
increasing pulse width continues to t2. With sufficient
output voltage, the clamp on the reference input controls
the output voltage. This is the interval between t2 and t3 in
Figure 3. At t3 the SS voltage exceeds the reference
voltage and the output voltage is in regulation. This method
provides a rapid and controlled output voltage rise.
FIGURE 4. OVERCURRENT OPERATION
Overcurrent Protection
The overcurrent function protects the converter from a
shorted output by using the upper MOSFETs on-resistance,
r
DS(ON)
to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
OCSET
)
programs the overcurrent trip level. An internal 200µA
(typical) current sink develops a voltage across R
OCSET
that
is reference to V
IN
. When the voltage across the upper
MOSFET (also referenced to V
IN
) exceeds the voltage
across R
OCSET
, the overcurrent function initiates a soft-start
sequence. The soft-start function discharges C
SS
with a
10µA current sink and inhibits PWM operation. The soft-start
function recharges C
SS
, and PWM operation resumes with
the error amplifier clamped to the SS voltage. Should an
overload occur while recharging C
SS
, the soft start function
inhibits PWM operation while fully charging C
SS
to 4V to
5
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