CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at 150°C may shorten the life of the part.
NOTES:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3.
θ
JC
, “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
SUPPLY CURRENT
Bias Supply Current
These specifications apply for T
A
= -40°C to +85°C, unless otherwise noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC+PVCC
PWM pin floating, V
VCC
= V
PVCC
= 5V
F
PWM
= 300kHz, V
VCC
= V
PVCC
= 5V
-
-
240
1.6
-
-
μA
mA
BOOTSTRAP DIODE
Forward Voltage
V
F
Forward bias current = 2mA
T
A
= 0°C to +70°C
Forward bias current = 2mA
T
A
= -40°C to +85°C
POWER-ON RESET
POR Rising
POR Falling
Hysteresis
PWM INPUT
Sinking Impedance
Source Impedance
Tri-State Rising Threshold
Tri-State Falling Threshold
Tri-State Shutdown Holdoff Time
SWITCHING TIME (Note 4, See Figure 1)
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
t
RU
t
RL
t
FU
t
FL
t
PDLU
t
PDLL
3nF Load
3nF Load
3nF Load
3nF Load
Outputs Unloaded
Outputs Unloaded
-
-
-
-
-
-
8.0
8.0
8.0
4.0
18
25
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
t
TSSHD
R
PWM_SNK
R
PWM_SRC
V
VCC
= V
PVCC
= 5V (250mV Hysteresis)
V
VCC
= V
PVCC
= 5V(300mV Hysteresis)
-
-
1.00
3.10
-
4.6
4.9
1.20
3.41
80
-
-
1.40
3.70
-
kΩ
kΩ
V
V
ns
-
2.6
-
3.4
3.0
400
4.2
-
-
V
V
mV
0.30
0.30
0.60
0.60
0.70
0.75
V
V
4
FN6395.0
November 22, 2006
ISL6610, ISL6610A
Electrical Specifications
PARAMETER
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
R
UG_SRC
R
UG_SNK
R
LG_SRC
R
LG_SNK
250mA Source Current
250mA Sink Current
250mA Source Current
250mA Sink Current
-
-
-
-
1.0
1.0
1.0
0.4
2.5
2.5
2.5
1.0
Ω
Ω
Ω
Ω
These specifications apply for T
A
= -40°C to +85°C, unless otherwise noted
(Continued)
SYMBOL
t
PDHU
t
PDHL
t
PTS
TEST CONDITIONS
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
MIN
-
-
-
TYP
18
23
20
MAX
-
-
-
UNITS
ns
ns
ns
Functional Pin Description
PACKAGE PIN #
SOIC
1
DFN
15
PIN
SYMBOL
PWM1
FUNCTION
The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
Bias and reference ground. All signals are referenced to this node.
Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
Power ground return of both low gate drivers.
No connection.
Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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