NCV7357
CAN FD Transceiver, High
Speed
Description
The NCV7357 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7357 is an addition to the CAN high−speed transceiver
family complementing NCV7344 CAN stand−alone transceivers and
previous generations such as AMIS42665, AMIS3066x, etc.
The NCV7357 guarantees additional timing parameters to ensure
robust communication at data rates beyond 1 Mbps to cope with CAN
flexible data rate requirements (CAN FD). These features make the
NCV7357 an excellent choice for all types of HS−CAN networks, in
nodes that require only a basic CAN capability.
Features
www.onsemi.com
SOIC−8
D SUFFIX
CASE 751AZ
DFNW8
MW SUFFIX
CASE 507AB
MARKING DIAGRAM
1
NV7357−X
ALYWG
G
8
NV7357−X
ALYWG
G
•
Compatible with ISO 11898−2:2016
•
CAN FD Timing Specified up to 5 Mbps
•
V
IO
Pin on NCV7357−3 Version Allowing Direct Interfacing with
•
•
•
•
•
•
•
•
•
•
•
3 V to 5 V Microcontrollers
Low Current, Listen Only Silent Mode
Low Electromagnetic Emission (EME) and High Electromagnetic
Immunity
Very Low EME without Common−mode (CM) Choke
No Disturbance of the Bus Lines with an Unpowered Node
Transmit Data (TxD) Dominant Timeout Function
Under All Supply Conditions the Chip Behaves Predictably
Very High ESD Robustness of Bus Pins, >8 kV System ESD Pulses
Thermal Protection
Bus Pins Short Circuit Proof to Supply Voltage and Ground
Bus Pins Protected Against Transients in an Automotive
Environment
These are Pb−free Devices
1
NV7357−X = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN ASSIGNMENT
1
TxD
GND
V
CC
RxD
NCV7357D1x
(Top View)
8
S
EP
CANH
CANL
NC (−
0)
3)
V
IO
(−
Quality
•
Wettable Flank Package for Enhanced Optical Inspection
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
TxD
GND
V
CC
RxD
1
8
S
CANH
CANL
NC (−
0)
V
IO
(−
3)
NCV
7357−
X
Typical Applications
2
7
•
Automotive
•
Industrial Networks
3
6
4
5
NCV7357MWx
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
March, 2019
−
Rev. 0
1
Publication Order Number:
NCV7357/D
NCV7357
NC
V
CC
5
V
CC
3
NCV7357−0
7
Thermal
Shutdown
1
TxD
CANH
Timer
V
CC
6
CANL
S
Mode
control
Driver
control
8
RxD
4
COMP
2
GND
Figure 1. NCV7357−0 Block Diagram
V
IO
V
CC
5
V
IO
3
NCV7357−3
7
Thermal
Shutdown
CANH
TxD
1
V
IO
Timer
6
S
8
CANL
Mode
control
Driver
control
RxD
4
COMP
2
GND
Figure 2. NCV7357−3 Block Diagram
www.onsemi.com
2
NCV7357
VBAT
IN
5V
−reg
OUT
V
CC
NC
5
3
V
CC
R
LT
= 60
W
CANH
CAN
BUS
CANL
R
LT
= 60
W
8
Micro−
controller
.
TxD
1
RxD
4
NCV 7357−0
2
S
7
6
GND
GND
Figure 3. Application Diagram NCV7357−0
VBAT
IN
5V
−reg
OUT
IN
3V
−reg
OUT
V
IO
5
3
V
CC
R
LT
= 60
W
CANH
CAN
BUS
CANL
R
LT
= 60
W
Micro−
controller
.
TxD
1
RxD
4
NCV7357−
3
2
S
8
7
6
GND
GND
Figure 4. Application Diagram NCV7357−3
Table 1. PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
5
6
7
8
Name
TxD
GND
V
CC
RxD
NC
V
IO
CANL
CANH
S
EP
Description
Transmit data input; low input
Ù
dominant driver; internal pull−up current
Ground
Supply voltage
Receive data output; dominant transmitter
Ù
low output
Not connected. On NCV7357−0 only
Digital Input / Output pins supply voltage. On NCV7357−3 only
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Silent mode control input; internal pull−up current
Exposed Pad. Recommended to connect to GND or left floating in application
(DFNW8 package only).
www.onsemi.com
3
NCV7357
FUNCTIONAL DESCRIPTION
High speed CAN FD transceiver
NCV7357 implements high−speed physical layer CAN
FD transceiver compatible with ISO11898−2, implementing
following optional features or alternatives:
•
Extended bus load range
Operating Modes
•
Transmit dominant timeout, long
•
Support of bit rates up to 5 Mbps
•
Normal Bus biasing
NCV7357 provides two modes of operation as illustrated
in Table 2. These modes are selectable through pin S.
Table 2. OPERATING MODES
Pin S
Low
Mode
Normal
Pin TxD
0
1
X
BUS
Dominant
Recessive
Dominant
(1)
Pin RxD
0
1
0
1
High
Silent
X
Recessive
1. CAN BUS driven by another transceiver on the BUS
2. ’X’ = don’t care
Power−off
Overtemperature Detection
This virtual mode is entered as soon as the V
CC
or V
IO
undervoltage condition is detected. The internal logic is
reset and the transceiver is disabled. CAN bus pins are kept
floating. As soon as both V
CC
and V
IO
voltages rise above
corresponding undervoltage recovery thresholds, the device
proceeds to Normal or Silent mode, depending on S pin
state.
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
Silent Mode
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds T
J(sd)
value. Because the transmitter dissipates most
of the power, the power dissipation and temperature of the
IC is reduced. All other IC functions continue to operate.
The transmitter off−state resets when the temperature
decreases below the shutdown threshold and pin TxD goes
high. The thermal protection circuit is particularly needed
when a bus line short circuits.
TxD Dominant Timeout Function
In the silent mode, the transmitter is disabled. The bus pins
are in recessive state independent of TxD input. Transceiver
listens to the bus and provides data to controller, but
controller is prevented from sending any data to the bus.
Power−off
CAN: off (no bias)
RxD: High−Z
TxD, S: High−Z
No UV
and S = High
S = High
S = Low
Any
mode
UV
detected
A TxD dominant timeout timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant timeout time t
dom(TxD)
defines the
minimum possible bit rate to 17 kbps.
Fail Safe Features
No UV
and S = Low
Normal mode
S = Low
CAN: Tx/Rx
CAN bias: V
CC
/2
Notes:
NCV7357−0
UV detected: V
CC
< V
UVDVCC
No UV:
V
CC
> V
UVDVCC
Silent mode
S = High
CAN: Rx only
CAN bias: V
CC
/2
NCV7357−3
UV detected: V
CC
< V
UVDVCC
and/or V
IO
< V
UVDVIO
No UV:
V
CC
> V
UVDVCC
and V
IO
> V
UVDVIO
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit
to either positive or negative supply voltage, although
power dissipation increases during this fault condition.
Detection of undervoltage on supply pin (V
CC
or V
IO
)
causes switching off device. After supply voltage is
recovered TxD pin must be first released to high to allow
sending dominant bits again.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
www.onsemi.com
4
NCV7357
Figure 7). Pins TxD and S are biased internally should the
input become disconnected. Pins TxD, S and RxD will be
floating, preventing reverse supply should the VCC supply
be removed.
The V
IO
pin (available only on NCV7357−3 version)
should be connected to microcontroller supply pin. By using
V
IO
supply pin shared with microcontroller the I/O levels
ABSOLUTE MAXIMUM RATINGS
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
SUP
V
CANH
V
CANL
V
CANH
−
CANL
V
I/O
V
esdHBM
V
esdCDM
V
esdIEC
Parameter
Supply voltage V
CC
, V
IO
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage between CANH and CANL
DC voltage at pin TxD, RxD, S
Electrostatic discharge voltage at all
pins, Component HBM
Electrostatic discharge voltage at all
pins, Component CDM
Electrostatic discharge voltage at pins
CANH and CANL,
System HBM (Note 6)
Voltage transients, pins CANH, CANL.
According to ISO7637−3, Class C
(Note 6)
(Note 3)
(Note 4)
(Note 5)
0 < V
CC
< 5.5 V; no time limit
0 < V
CC
< 5.5 V; no time limit
Conditions
Min.
−0.3
−42
−42
−42
−0.3
−6
Max.
+6.0
+42
+42
+42
+6.0
+6
Unit
V
V
V
V
V
kV
between microcontroller and transceiver are properly
adjusted. See Figure 4.
Definitions
V
IO
Supply Pin
All voltages are referenced to GND (pin 2). Positive
currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current
is flowing out of the pin.
−750
+750
V
−8
−100
+8
kV
V
V
schaff
test pulses 1
test pulses 2a
test pulses 3a
test pulses 3b
+75
−150
+100
150
−55
−40
2
1
+150
+170
V
V
V
mA
°C
°C
−
−
Latch−up
T
stg
T
J
MSL
SOIC
MSL
DFN
Static latch−up at all pins
Storage temperature
Maximum junction temperature
Moisture sensitivity level for SOIC−8
Moisture sensitivity level for DFNW8
(Note 7)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF
capacitor through a 1.5 kW resistor
4. Standardized charged device model ESD pulses when tested according to AEC−Q100−011
5. System human body model electrostatic discharge (ESD) pulses in accordance to IEC 61000−4−2. Equivalent to discharging a 150 pF
capacitor through a 330
W
resistor referenced to GND
6. Results were verified by external test house
7. Static latch−up immunity: Static latch−up protection level when tested according to EIA/JESD78
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
