EEPROM
AS8E128K32
128K x 32 EEPROM
EEPROM Memory Array
AVAILABLE AS MILITARY
SPECIFICATIONS
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•
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•
•
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•
PIN ASSIGNMENT
(Top View)
66 Lead PGA
(Pins 8, 21, 28, 39 are no connects on the PN package)
SMD 5962-94585
MIL-STD-883
Access times of 120, 140, 150, 200, 250, and 300 ns
Built in decoupling caps for low noise operation
Organized as 128K x32; User configurable
as 256K x16 or 512K x8
Operation with single 5 volt supply
Low power CMOS
TTL Compatible Inputs and Outputs
Operating Temperature Ranges:
Military: -55
o
C to +125
o
C
Industrial: -40
o
C to +85
o
C
FEATURES
66 Lead PGA
(Pins 8, 21, 28, 39 are grounds on the P package)
OPTIONS
•
MARKINGS
-120
-140
-150
-200
-250
-300
Q
Q3
P
PN
68 Lead CQFP
3
4
•
Timing
120 ns
140 ns
150 ns
200 ns
250 ns
300 ns
Package
Ceramic Quad Flat Pack
Ceramic Quad Flat Pack
Pin Grid Array- 8 Series
Pin Grid Array- 8 Series
GENERAL DESCRIPTION
The AS8E128K32 is a 4 Megabit EEPROM Module organized
as 128K x 32 bit. User configurable to 256K x16 or 512Kx 8. The
module achieves high speed access, low power consumption and high
reliability by employing advanced CMOS memory technology.
The military grade product is manufactured in compliance to the
SMD and MIL-STD 883, making the AS8E128K32 ideally suited for
military or space applications.
The module is offered in a 1.075 inch square ceramic pin grid
array substrate. This package design provides the optimum space
saving solution for boards that accept through hole packaging.
The module is also offered as a 68 lead 0.990 inch square ceramic
quad flat pack. It has a max. height of 0.200 inch. This package de-
sign is targeted for those applications which require low profile SMT
Packaging.
For more products and information
please visit our web site at
www.micross.com
AS8E128K32
Rev. 8.1 01/10
Micross Components reserves the right to change products or specifications without notice.
1
EEPROM
AS8E128K32
DEVICE IDENTIFICATION
An extra 128 bytes of EEPROM memory is available on each
die for user identification. By raising A9 to 12V + 0.5V and using
address locations 1FF80H to 1FFFFH the bytes may be written to
or read from in the same manner as the regular memory array.
of the last byte written will result in the complement of the written data
to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle may begin.
DATA Polling may begin at anytime during the write cycle.
TOGGLE BIT
DEVICE OPERATION
The 128K x 32 EEPROM memory solution is an electrically
erasable and programmable memory module that is accessed like a
Static RAM for the read or write cycle without the need for external
components. The device contains a 128-byte-page register to allow
writing of up to 128 bytes of data simultaneously. During a write cycle,
the address and 1 to 128 bytes of data are internally latched, freeing
the address and data bus for other operations. Following the initia-
tion of a write cycle, the device will automatically write the latched
data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has
been detected a new access for a read or write can begin.
In addition to DATA Polling the module provides another method
for determining the end of a write cycle. During the write operation,
successive attempts to read data from the device will result in I/O6
of the accessed die toggling between one and zero. Once the write
has completed, I/O6 will stop toggling and valid data will be read.
Reading the toggle bit may begin at any time during the write cycle.
DATA PROTECTION
If precautions are not taken, inadvertent writes may occur during
transitions of the host power supply. The E
2
module has incorporated
both hardware and software features that will protect the memory
against inadvertent writes.
READ
The memory module is accessed like a Static RAM. When CE\
and OE\ are low and WE\ is High, the data stored at the memory loca-
tion determined by the address pins is asserted on the outputs. The
module can be read as a 32 bit, 16 bit or 8 bit device. The outputs are
put in the high impedance state when either CE\ or OE\ is high. This
dual-line control gives designers flexibility in preventing bus conten-
tion in their system.
HARDWARE PROTECTION
Hardware features protect against inadvertent writes to the module
in the following ways: (a) Vcc sense - if Vcc is below 3.8 V (typical)
the write function is inhibited; (b) Vcc power-on delay - once Vcc has
reached 3.8 V the device will automatically time out 5 ms (typical)
before allowing a write; (c) write inhibit - holding any one of OE\ low,
CE\ high or WE\ high inhibits write cycles; (d) noise filter - pulses of
less than 15 ns (typical) on the WE\ or CE\ inputs will not initiate a
write cycle.
BYTE WRITE
A low pulse on the WE\ or CE\ input with CE\ or WE\ low (re-
spectively) and OE\ high initiates a write cycle. The address is latched
on the falling edge of CE\ or WE\, whichever occurs last. The data is
latched by the first rising edge of CE\ or WE\. Once a BWDW (byte,
word or double word) write has been started it will automatically time
itself to completion.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been imple-
mented on the memory module. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user and is shipped with SDP dis-
abled, SDP is enabled by the host system issuing a series of three write
commands; three specific bytes of data are written to three specific
addresses (refer to Software Data Protection Algorithm). After writing
the three byte command sequence and after t
WC
the entire module will
be protected from inadvertent write operations. It should be noted,
that once protected the host may still perform a byte of page write to
the module. This is done by preceding the data to be written by the
same three byte command sequence used to enable SDP. Once set,
SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the 128K x
32 EEPROM during power-up and Power-down conditions. All com-
mand sequences must conform to the page write timing specifications.
The data in the enable and disable command sequences is not written
to the device and the memory addresses used in the sequence may be
written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the
three byte command sequence will start the internal write timers. No
data will be written to the device; however, for the duration of t
WC
,
read operations will effectively be polling operations.
Micross Components reserves the right to change products or specifications without notice.
PAGE WRITE
The page write operation of the 128K x 32 EEPROM allows 1
to 128 BWDWs of data to be written into the device during a single
internal programming period. Each new BWDW must be written
within 150-μ sec (t
BLC
) of the previous BWDW. If the t
BLC
limit is
exceeded the memory module will cease accepting data and commence
the internal programming operation. For each WE high to low transi-
tion during the page write operation, A7-A16 must be the same.
The A0-A6 inputs are used to specify which bytes within the page
are to be written. The bytes may be loaded in any order and may be
altered within the same load period. Only bytes which are specified
for writing will be written; unnecessary cycling of other bytes within
the page does not occur.
DATA POLLING
This memory module features DATA Polling to indicate the end
of a write cycle. During a byte or page write cycle an attempted read
AS8E128K32
Rev. 8.1 01/10
2
EEPROM
AS8E128K32
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc .......................................................................-.5V to +7.0V
Storage Temperature ....................... ....................-65°C to +150°C
Voltage on any Pin Relative to Vss.....................-.5V to Vcc+1 V
Max Junction Temperature**............................................+150°C
Thermal Resistance junction to case (θ
JC
):
Package Type Q...............................................11.3° C/W
Package Type P & PN.......................................2.8° C/W
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Ex-
posure to absolute maximum rating conditions for extended
periods may affect reliability.
**Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humid-
ity (plastics).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C<T
A
<125
o
C or -40
o
C to +85
o
C; Vcc = 5V + 10%)
μΑ
μΑ
PARAMETER
Power Supply Current:
Operating
CONDITIONS
CE\<V
IL
; V
CC
=MAX,
f = MAX = 1/t
RC
(MIN)
Outputs Open
CE\>V
IH
; All Other Inputs
<V
IL
or >V
IH
; V
CC
=MAX,
f =0 Hz
CE\>V
CC
-0.2V; V
CC
=MAX,
V
IL
<V
SS
+0.2V or
V
IH
>V
CC
-0.2V; f = 0 Hz
CE\=V
CC
, OE\=V
IH
;
I/O 0 through 31 = open;
Input=V
CC
=5.5Vdc.;
A0 through A16 change at 5 MHz;
CMOS levels
SYM
I
cc
MAX
For All Speed Options UNITS
250
mA
I
SBT1
15
mA
Power Supply Current:
Standby
I
SBT2
1
mA
I
SBT3
5
mA
AS8E128K32
Rev. 8.1 01/10
Micross Components reserves the right to change products or specifications without notice.
3
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