ADVANCE INFORMATION
Am29LV160M
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit
TM
3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s
Manufactured on 0.23 µm MirrorBit
TM
process
technology
— Fully compatible with Am29LV160D device
s
High performance
— Access times as fast as 70 ns
s
Ultra low power consumption (typical values at
5 MHz)
— 400 nA Automatic Sleep mode current
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
s
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 1,000,000 write cycle guarantee
per sector
s
20-year data retention at 125°C
— Reliable operation for the life of the system
s
Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
— 64-ball Fortified BGA
s
CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
s
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion (not available
on 44-pin SO)
s
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25974
Rev:
A
Amendment/1
Issue Date:
July 3, 2002
GENERAL DESCRIPTION
The Am29LV160M is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes or 1,048,576
words. The device is offered in 48-ball FBGA, 44-pin
SO, and 48-pin TSOP packages. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data
appears on DQ7–DQ0. This device is designed to be
programmed in-system with the standard system 3.0
volt V
CC
supply. A 12.0 V V
PP
or 5.0 V
CC
are not
required for write or erase operations. The device can
also
be
programmed
in
standard
EPROM programmers.
The device offers access times of 70, 90, and 120 ns,
allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The Am29LV160M is entirely command set compatible
with the
JEDEC single-power-supply Flash stan-
dard.
Commands are written to the command register
using standard microprocessor write timings. Register
contents serve as input to an internal state-machine
that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
2
Am29LV160M
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV160M Device Bus Operations ..............................10
RY/BY#: Ready/Busy# ............................................................ 27
DQ6: Toggle Bit I .................................................................... 27
DQ2: Toggle Bit II ................................................................... 27
Reading Toggle Bits DQ6/DQ2 ............................................... 27
Figure 6. Toggle Bit Algorithm........................................................ 28
DQ3: Sector Erase Timer ....................................................... 29
Table 10. Write Operation Status ................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 7. Maximum Negative Overshoot Waveform ...................... 30
Figure 8. Maximum Positive Overshoot Waveform........................ 30
Word/Byte Configuration ........................................................ 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Sector Address Tables (Am29LV160MT) .........................13
Table 3. Sector Address Tables (Am29LV160MB) .........................14
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Test Setup....................................................................... 33
Table 11. Test Specifications ......................................................... 33
Figure 10. Input Waveforms and Measurement Levels ................. 33
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Read Operations .................................................................... 34
Figure 11. Read Operations Timings ............................................. 34
Autoselect Mode ..................................................................... 15
Table 4. Am29LV160M Autoselect Codes (High Voltage Method) .15
Hardware Reset (RESET#) .................................................... 35
Figure 12. RESET# Timings .......................................................... 35
Sector Protection/Unprotection ............................................... 15
Temporary Sector Unprotect .................................................. 16
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-System Single High Voltage Sector Protect/Unprotect Al-
gorithms .......................................................................................... 17
Word/Byte Configuration (BYTE#) ........................................ 36
Figure 13. BYTE# Timings for Read Operations............................ 36
Figure 14. BYTE# Timings for Write Operations............................ 36
Erase/Program Operations ..................................................... 37
Figure 15. Program Operation Timings..........................................
Figure 16. Chip/Sector Erase Operation Timings ..........................
Figure 17. Data# Polling Timings (During Embedded Algorithms).
Figure 18. Toggle Bit Timings (During Embedded Algorithms)......
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................
Figure 20. Temporary Sector Unprotect/Timing Diagram ..............
Figure 21. Sector Protect/Unprotect Timing Diagram ....................
Figure 22. Alternate CE# Controlled Write Operation Timings ......
38
39
40
40
41
41
42
44
Common Flash Memory Interface (CFI) . . . . . . . 18
Table 5. CFI Query Identification String ..........................................18
Table 6. System Interface String .....................................................18
Table 7. Device Geometry Definition ..............................................19
Table 8. Primary Vendor-Specific Extended Query ........................19
Hardware Data Protection ...................................................... 20
Low V
CC
Write Inhibit .............................................................. 20
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 21
Reading Array Data ................................................................ 21
Reset Command ..................................................................... 21
Autoselect Command Sequence ............................................ 21
Word/Byte Program Command Sequence ............................. 21
Unlock Bypass Command Sequence ..................................... 22
Figure 3. Program Operation .......................................................... 22
Chip Erase Command Sequence ........................................... 22
Sector Erase Command Sequence ........................................ 23
Erase Suspend/Erase Resume Commands ........................... 23
Figure 4. Erase Operation............................................................... 24
Command Definitions ............................................................. 25
Table 9. Am29LV160M Command Definitions ................................25
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling ................................................................. 26
Figure 5. Data# Polling Algorithm ................................................... 26
Erase and Programming Performance . . . . . . . 45
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46
TS 048—48-Pin Standard TSOP ............................................ 46
TSR048—48-Pin Reverse TSOP ........................................... 47
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm ................................................................................ 48
SO 044—44-Pin Small Outline Package ................................ 49
LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm
Package .................................................................................. 50
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision A (June 24, 2002) .................................................... 51
Revision A + 1 (July 3, 2002) .................................................. 51
Am29LV160M
3
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Voltage Range: V
CC
= 2.7–3.6 V
-70
70
70
30
Am29LV160M
-90
90
90
35
-120
120
120
50
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ15 (A-1)
WE#
BYTE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A19
4
Am29LV160M
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Am29LV160M
5
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