DATASHEET
LOCO™ PLL CLOCK MULTIPLIER
Description
The ICS501A LOCO
TM
is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 200
MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
ICS501A
Features
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Packaged as 8-pin SOIC (Pb-free) or die
IDT’s lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of up to 27 MHz
Input clock frequency of up to 50 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Nine selectable frequencies
Operating voltage of 3.3 V
Tri-state output for board level testing
25 mA drive capability at TTL levels
Ideal for oscillator replacement
Optimized for output frequencies of up to 200 MHz
(166 MHz maximum for industrial temperature
version)
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Industrial temperature version available
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Advanced, low power CMOS process
Block Diagram
VDD
S1:0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
PLL Clock
Multiplier
Circuitry
and ROM
CLK
Optional crystal capacitors
GND
OE
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
1
ICS501A
REV F 051310
ICS501A
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Clock Output Table
S1 S0
0
0
M
1
0
M
1
0
M
1
CLK
4X input
5.333X input
5X input
10X input
2X input
12X input
6X input
3X input
8X input
Minimum Input (MHz)
15
12
12
6
30
5
10
20
10
X1/ I CLK
VDD
GND
S1
1
2
3
4
8
7
6
5
X2
OE
S0
CLK
0
0
M
M
M
1
1
1
8 Pi n ( 150 mi l ) SOI C
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
XI/ICLK
VDD
GND
S1
CLK
S0
OE
X2
Pin
Type
Input
Power
Power
Tri-level Input
Output
Tri-level Input
Input
Output
Connect to +3.3 V.
Connect to ground.
Pin Description
Crystal connection or clock input.
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up
resistor.
Crystal connection. Leave unconnected for clock input.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
2
ICS501A
REV F 051310
ICS501A
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS501A must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS501A to minimize lead inductance. No
external power supply filtering is required for the
ICS501A.
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2 = 8].
Series Termination Resistor
A 33Ω terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS501A. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
°
C
V
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
3
ICS501A
REV F 051310
ICS501A
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=3.3 V ±10%
, Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK only
Input Low Voltage, ICLK only
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
IDD Operating Supply Current, 20
Short Circuit Current
On-Chip Pull-up Resistor
Input Capacitance, S1, S0, and OE
Nominal Output Impedance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Conditions
ICLK (pin 1)
ICLK (pin 1)
OE (pin 7)
OE (pin 7)
S0, S1
S0, S1
I
OH
= -12 mA
I
OL
= 12 mA
No load, 100M
CLK output
Pin 7
Pins 4, 6, 7
Min.
3.0
(VDD/2)+1
Typ.
Max.
3.6
(VDD/2)-1
Units
V
V
V
V
V
V
V
V
V
mA
mA
kΩ
pF
Ω
2.0
0.8
VDD-0.5
0.5
2.4
0.4
20
+70
270
4
20
AC Electrical Characteristics
VDD = 3.3 V ±10%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 3.0 to 3.6 V
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
PLL Bandwidth
Output Enable Time, OE high to
output on
Output Disable Time, OE low to
tri-state
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Note 1: Measured with 15 pF load.
t
ja
t
js
Deviation from mean
Symbol
F
IN
F
IN
F
OUT
t
OR
t
OF
t
OD
Conditions
see page 2
see page 2
0° C to +70° C
-40° C to +85° C
0.8 to 2.0 V, Note 1
2.0 to 8.0 V, Note 1
1.5 V, up to 160
MHz
Min.
Typ.
Max.
27
50
200
166
Units
MHz
MHz
MHz
MHz
ns
ns
1
1
45
120
50
50
+70
25
49-51
55
%
kHz
ns
ns
ps
ps
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
4
ICS501A
REV F 051310
ICS501A
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Package Outline and Package Dimensions
(8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Symbol
Min
Max
Inches
Min
Max
E
INDEX
AREA
H
1 2
D
A
A1
B
C
D
E
e
H
h
L
α
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0
°
8
°
h x 45
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0
°
8
°
A
A1
C
-C-
e
B
SEATING
PLANE
L
.10 (.004)
C
Ordering Information
Part / Order Number
501AMLF
501AMLFT
501AMILF
501AMILFT
501A-DWF
501A-DPK
Marking
501AMLF
501AMLF
501AIML
501AIML
-
-
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Die on uncut, probed wafers
Tested die in waffle pack
Package
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER
5
ICS501A
REV F 051310
微控制器 MCU
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