a
FEATURES
Monolithic 12-Bit 5 MSPS A/D Converter
Low Noise: 0.17 LSB RMS Referred to Input
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: 73 dB
Power Dissipation: 1.03 W
Complete: On-Chip Track-and-Hold Amplifier and
Voltage Reference
Pin Compatible with the AD872
Twos Complement Binary Output Data
Out of Range Indicator
28-Lead Side Brazed Ceramic DIP or 44-Terminal
Surface Mount Package
V
INA
V
INB
Complete 12-Bit 5 MSPS
Monolithic A/D Converter
AD871
FUNCTIONAL BLOCK DIAGRAM
AV
DD
AGND AV
SS
DV
DD
DGND
*
DRV
DD
*
DRGND
AD871
T/H
A/D
4
D/A
T/H
A/D
4
D/A
T/H
A/D
3
D/A
A/D
4
CLOCK
REF IN
REF OUT
+2.5V
REFERENCE
CORRECTION LOGIC
OUTPUT BUFFERS
12
REF OUT
*
OUTPUT
ENABLE
OTR
*MSB
MSB–BIT
12
(LSB)
*ONLY AVAILABLE ON 44 -TERMINAL SURFACE MOUNT PACKAGE
PRODUCT DESCRIPTION
The AD871 is a monolithic 12-bit, 5 MSPS analog-to-digital
converter with an on-chip, high performance track-and-hold
amplifier and voltage reference. The AD871 uses a multistage
differential pipelined architecture with error correction logic to
provide 12-bit accuracy at 5 MSPS data rates and guarantees no
missing codes over the full operating temperature range. The
AD871 is a redesigned variation of the AD872 12-bit, 10 MSPS
ADC, optimized for lower noise in applications requiring sam-
pling rates of 5 MSPS or less. The AD871 is pin compatible
with the AD872, allowing the parts to be used interchangeably
as system requirements change.
The low-noise input track-and-hold (T/H) of the AD871 is ide-
ally suited for high-end imaging applications. In addition, the
T/H’s high input impedance and fast settling characteristics
allow the AD871 to easily interface with multiplexed systems
that switch multiple signals through a single A/D converter. The
dynamic performance of the input T/H also renders the AD871
suitable for sampling single channel inputs at frequencies up to
and beyond the Nyquist rate. The AD871 provides both refer-
ence output and reference input pins, allowing the onboard ref-
erence to serve as a system reference. An external reference can
also be chosen to suit the dc accuracy and temperature drift
requirements of the application. A single clock input is used to
control all internal conversion cycles. The digital output data is
presented in twos complement binary output format. An out-of-
range signal indicates an overflow condition, and can be used
with the most significant bit to determine low or high overflow.
The AD871 is fabricated on Analog Devices’ ABCMOS-1 pro-
cess, which uses high speed bipolar and CMOS transistors on a
single chip. High speed, precision analog circuits are now com-
bined with high density logic circuits.
The AD871 is packaged in a 28-lead ceramic DIP and a
44-terminal leadless ceramic surface mount package and is
specified for operation from 0°C to +70°C and –55°C to
+125°C.
PRODUCT HIGHLIGHTS
The AD871 offers a complete single-chip sampling 12-bit,
5 MSPS analog-to-digital conversion function in a 28-lead DIP
or 44-terminal leadless ceramic surface mount package (LCC).
Low Noise—The
AD871 features 0.17 LSB referred-to-input
noise, producing essentially a “1 code wide” histogram for a
code-centered dc input.
Low Power—The
AD871 at 1.03 W consumes a fraction of the
power of presently available hybrids.
On-Chip Track-and-Hold (T/H)—The
low noise, high imped-
ance T/H input eliminates the need for external buffers and can
be configured for single ended or differential inputs.
Ease of Use—The
AD871 is complete with T/H and voltage ref-
erence and is pin-compatible with the AD872 (12-bit, 10 MSPS
monolithic ADC).
Out of Range (OTR)—The
OTR output bit indicates when the
input signal is beyond the AD871’s input range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
AD871
AC SPECIFICATIONS
(T
MIN
to T
MAX
with AV
DD
= +5 V, DV
DD
= +5 V, DRV
DD
= +5 V, AV
SS
= –5 V, f
SAMPLE
= 5 MSPS, unless otherwise
noted)
1
J Grade
SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)
f
INPUT
= 750 kHz
f
INPUT
= 1 MHz
f
INPUT
= 2.49 MHz
TOTAL HARMONIC DISTORTION (THD)
f
INPUT
= 750 kHz
f
INPUT
= 1 MHz
f
INPUT
= 2.49 MHz
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
INPUT
= 750 kHz
f
INPUT
= 1 MHz
f
INPUT
= 2.49 MHz
INTERMODULATION DISTORTION (IMD)
2
Second Order Products
Third Order Products
FULL POWER BANDWIDTH
SMALL SIGNAL BANDWIDTH
APERTURE DELAY
APERTURE JITTER
ACQUISITION TO FULL-SCALE STEP
OVERVOLTAGE RECOVERY TIME
68
66
63
60
–72
–69
–64
–62
73
70
62
–80
–73
15
15
6
16
80
80
S Grade
68
66
62
60
–72
–69
–63
–62
73
70
62
–80
–73
15
15
6
16
80
80
Units
dB typ
dB typ
dB min
dB typ
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
MHz typ
MHz typ
ns typ
ps rms typ
ns typ
ns typ
NOTES
1
f
IN
amplitude = –0.5 dB full scale unless otherwise indicated. All measurements referred to a 0 dB (1 V pk) input signal unless otherwise indicated.
2
fa = 1.0 MHz, fb = 0.95 MHz with f
SAMPLE
= 5 MHz.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
with AV
DD
= +5 V, DV
DD
= +5 V, AV
SS
= –5 V unless otherwise noted)
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
C
OUT
IZ
J, S Grades
+2.0
+0.8
±
115
±
115
5
+2.4
+0.4
5
±
10
Units
V min
V max
µA
max
µA
max
pF typ
V min
V max
pF typ
µA
max
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= DV
DD
)
Low Level Input Current (V
IN
= 0 V)
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage (I
OH
= 0.5 mA)
Low Level Output Voltage (I
OL
= 1.6 mA)
Output Capacitance
Leakage (Three-State, LCC Only)
Specifications subject to change without notice.
REV. A
–3–
AD871
SWITCHING SPECIFICATIONS
Parameter
Clock Period
l
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Clock Duty Cycle
2
Output Delay
Pipeline Delay (Latency)
Data Access Time (LCC Package Only)
3
Output Float Delay (LCC Package Only)
3
(T
MIN
to T
MAX
with AV
DD
= +5 V, DV
DD
= +5 V, DRV
DD
= +5 V, AV
SS
= –5 V; V
IL
= 0.8 V,
V
IH
= 2.0 V, V
OL
= 0.4 V and V
OH
= 2.4 V)
Symbol
t
C
t
CH
t
CL
t
OD
t
DD
t
HL
J, S Grades
200
95
95
40
60
10
3
50
50
Units
ns min
ns min
ns min
% min (50% typ)
% max
ns min (20 ns typ)
Clock Cycles
ns typ (100 pF Load)
ns typ (10 pF Load)
NOTES
1
Conversion rate is operational down to 10 kHz without degradation in specified performance.
2
For clock periods of 200 ns or greater, see Clock Input section.
3
See section on Three-State Outputs for timing diagrams and application information.
Specifications subject to change without notice.
N
VIN
N+1
t
C
CLOCK
N
N+1
t
CH
BIT 2–12
MSB,
OTR
t
CL
DATA
N
t
OD
DATA
N+1
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1
Parameter
AV
DD
AV
SS
DV
DD
, DRV
DD
DRV
DD2
DRGND
2
AGND
AV
DD
Clock Input, OEN
Digital Outputs
V
INA
, V
INB
REF IN
REF IN
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With Respect to
AGND
AGND
DGND, DRGND
DV
DD
DGND
DGND
DV
DD
DGND
DGND
AGND
AGND
Min
–0.5
–6.5
–0.5
–6.5
–0.3
–1.0
–6.5
–0.5
–0.5
–6.5
AV
SS
–65
Max
+6.5
+0.5
+6.5
+6.5
+0.3
+1.0
+6.5
DV
DD
+ 0.5
DV
DD
+ 0.3
+6.5
AV
DD
+150
+150
+300
Units
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
Volts
°C
°C
°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
2
LCC Package Only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD871 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD871
PIN FUNCTION DESCRIPTIONS
Symbol
V
INA
V
INB
AV
SS
AV
DD
AGND
DGND
DV
DD
BIT 12 (LSB)
BIT 2–BIT 11
MSB
OTR
CLK
REF OUT
REF GND
REF IN
BIT 1 (MSB)
DRV
DD
DRGND
DIP
Pin No.
1
2
3, 25
4
5, 24
6, 23
7, 22
8
18–9
19
20
21
26
27
28
N/A
N/A
N/A
LCC
Pin No.
1
2
5, 40
6, 38
9, 36
10
33
16
26–17
29
30
31
41
42
43
27
12, 32
11, 34
Type
AI
AI
P
P
P
P
P
DO
DO
DO
DO
DI
AO
AI
AI
DO
P
P
Name and Function
(+) Analog Input Signal on the differential input amplifier.
(–) Analog Input Signal on the differential input amplifier.
–5 V Analog Supply.
+5 V Analog Supply.
Analog Ground.
Digital Ground.
+5 V Digital Supply.
Least Significant Bit.
Data Bits 2 through 11.
Inverted Most Significant Bit. Provides twos complement output
data format.
Out of Range is Active HIGH on the leading edge of code 0 or
the trailing edge of code 4096. See Output Data Format Table III.
Clock Input. The AD871 will initiate a conversion on the rising
edge of the clock input. See the Timing Diagram for details.
+2.5 V Reference Output. Tie to REF IN for normal operation.
Reference Ground.
Reference Input. +2.5 V input gives
±
1 V full-scale range.
Most Significant Bit.
+5 V Digital Supply for the output drivers.
Digital Ground for the output drivers.
(See section on Power Supply Decoupling for details on
DRV
DD
and DRGND.)
Output Enable. See the Three State Output Timing Diagram for details.
No Connect.
OEN
NC
N/A
N/A
13
3, 4, 7, 8, 14, 15,
28, 35, 37, 39, 44
DI
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power; N/A = Not Available on 28-lead DIP, available only on
44-terminal surface mount package.
PIN CONFIGURATIONS
28-Lead Side Brazed Ceramic DIP
V
INA
V
INB
AV
SS
AV
DD
AGND
DGND
DV
DD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
REF IN
REF GND
REF OUT
AV
SS
AGND
NC
7
NC
AGND
DGND
DRGND
8
9
10
11
44-Terminal LCC
REF IN
REF GND
REF OUT
AV
DD
AV
SS
AV
SS
39
NC
38
AV
DD
37
NC
36
AGND
35
NC
34
DRGND
33
DV
DD
32
DRV
DD
31
CLK
30
OTR
29
MSB
18 19 20 21 22 23 24 25 26 27 28
V
INB
2
V
INA
1
NC
NC
6
5
4
3
44 43 42 41 40
PIN 1
IDENTIFIER
AD871
TOP VIEW
(Not to Scale)
DGND
DV
DD
CLK
OTR
MSB
BIT 2
BIT 3
BIT 4
BIT 5
AD871
TOP VIEW
(Not to Scale)
DRV
DD 12
OEN
13
NC
14
NC
15
BIT 12 (LSB)
16
BIT 11
17
NC
NC = NO CONNECT
REV. A
–5–
BIT 1 (MSB)
NC
BIT 10
BIT 9
BIT 8
BIT 7
BIT 5
BIT 4
BIT 3
BIT 6
BIT 2
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