HY29F200T/B Series
2 Megabit 5.0 volt-only Sector Erase Flash Memory
KEY FEATURES
·
5.0 V ± 10% Read, Program, and Erase
- Minimizes system-level power requirements
·
High performance
-
70 ns access time
·
Compatible with JEDEC-Standard Commands
- Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
·
Minimum 100,000 Program/Erase Cycles
·
Sector Erase Architecture
- One 16 Kbytes, two 8 Kbytes, one 32 Kbytes,
and three 64 Kbytes
- Any combination of sectors can be erased
concurrently; also supports full chip erase
·
Erase Suspend/Resume
- Suspend a sector erase operation to allow a
data read in a sector not being erased within the
same device
·
Ready//Busy
- RY//BY ourput pin for detection of
programming or erase cycle completion
·
/RESET
- Hardware pin resets the internal state machine
to the read mode
·
Internal Erase Algorithms
- Automatically erases a sector, any combination
of sectors, or the entire chip
·
Internal Programming Algorithms
- Automatically programs and verifies data at a
specified address.
·
Low Power Consumption
- 20 mA typical active read current for Byte Mode
- 28 mA typical active read current for Word Mode
- 30 mA typical write/erase current
·
Sector Protection
- Hardware method disables any combination
of sectors from a program or erase operation
·
Boot Code Sector Architecture
DESCRIPTION
The HY29F200 is an 2 Megabit, 5.0 volt-only CMOS
Flash memory device organized as a 256 Kbytes
of 8 bits each, or 128 Kbytes of 16 bits each. The
device is offered in standard 44-pin PSOP and 48-
pin TSOP packages. It is designed to be pro-
grammed and erased in-system with a 5.0 volt
power-supply and can also be reprogrammed in
standard PROM programmers.
The HY29F200 offers access times of 70ns, 90 ns,
120 ns and 150 ns. The device has separate chip
enable (/CE), write enable (/WE) and output enable (/
OE) controls. Hyundai Flash memory devices reli-
ably store memory data even after 100,000 pro-
gram/erase cycles.
The HY29F200 is entirely pin and command set com-
patible with the JEDEC standard for 2 Megabit Flash
memory devices. The commands are written to the
command register using standard microprocessor
write timings. Register contents serve as input to
an internal state-machine which controls the erase
and programming circuitry. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and eraseoperations.
The HY29F200 is programmed by executing the pro-
gram command sequence. This will start the inter-
nal byte/word programming algorithm that automati-
cally times the program pulse width and also veri-
fies the proper cell margin. Erase is accomplished
by executing either the sector erase or chip erase
command sequence. This will start the internal
erasing algorithm that automatically times the
erase pulse width and also verifies the proper cell
margin. No preprogramming is required prior to ex-
ecution of the internal erase algorithm. Sectors of
the HY29F200 Flash memory array are electrically
erased via Fowler-Nordheim tunneling. Bytes/words
are programmed one byte/word at a time using a
hot electron injection mechanism.
The HY29F200 features a sector erase architec-
ture. The device memory array is divided into one
16 Kbyte, two 8 Kbytes, one 32 Kbytes, and three
64 Kbytes. The sectors can be erased individually
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility
for use of circuits described. No patent licences are implied.
Rev.03/Aug.97
Hyundai Semiconductor
or in groups without affecting the data in other sec-
tors. The multiple sector erase and full chip erase
capabilities add flexibility to altering the data in the
device. To protect data in the device from acciden-
tal program and erase, the device also has a sec-
tor protect function. This function hardware write
protects the selected sector(s). The sector protect
and sector unprotect features can be enabled in a
PROM programmer.
The HY29F200 needs a single 5.0 volt power-sup-
ply for read, program and erase operation. Inter-
nally generated and well regulated voltages are pro-
vided for the program and erase operation. A low
Vcc detector inhibits write operations on the loss of
power. The end of program or erase is detected by
the Ready/Busy status pin, /Data Polling of DQ7 or
by the Toggle Bit I feature on DQ6. Once the pro-
gram or erase cycle has been successfully com-
pleted, the device internally resets to the Read mode.
The HY29F200 also has a hardware /RESET pin.
Driving the /RESET pin low during execution of an
Internal Programming or Erase command will ter-
minate the operation and reset the device to the
Read mode. The /RESET pin may be tied to the
system reset circuitry, so that the system will have
access to boot code upon completion of the sys-
tem reset, even if the Flash device is in the pro-
cess of an Internal Programming or Erase opera-
tion. If the device is reset using the /RESET pin dur-
ing an Internal Programming or Erase operation,
the data in the address locations on which the in-
ternal state machine is operating will be erroneous.
Thus, these address locations will need rewriting
after the device is reset.
BLOCK DIAGRAM
V cc
V ss
R Y//B Y
B uffer
D Q 0 -D Q 15
E rase V oltage
G en erato r
Input /O utpu t
B uffers
WE
B Y TE
R E SE T
S tate
C ontrol
C om m and
R egister
P G M V oltage
G en erato r
C hip E nable
O u tput E nable
Log ic
CE
OE
S TB
D ata Latch
S TB
Y -D ecoder
V cc D etector
A 0-A16
A -1
A ddress
Latch
Y -G ating
T im e r
C ell M atrix
X -D ecoder
2
HY29F200
BUS OPERATION
Table 1. Bus Operations (/BYTE = V
IH
)
(1)
OPERATION
Electronic ID Manufacturer
(2)
Electronic ID Device
(2)
Read
(3)
/CE
L
L
L
H
X
L
L
L
L
X
(2)
/OE
L
L
L
X
X
H
H
V
ID
L
X
/WE
H
H
H
X
X
H
L
L
H
X
A0
L
H
A0
X
X
X
A0
X
L
X
A1
L
L
A1
X
X
X
A1
X
H
X
A6
L
L
A6
X
X
X
A6
X
L
X
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
V
ID
X
DQ0-DQ15
Code
Code
D
OUT
High Z
High Z
High Z
D
IN
(4)
/RESET
H
H
H
H
L
X
H
H
H
V
ID
Standby
Hardware /RESET
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
Temporary Sector Unprotect
X
Code
X
Notes:
1. L = V
IL
, H = V
IH
, X = Don’t Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be V
IL
if /CE is V
IL
, /OE at V
IH
initiates the write operations.
4. Refer to Table 6 for valid D
IN
during a write operation.
Table 2. Bus Operations (/BYTE = V
IL
)
(1)
OPERATION
Electronic ID Manufacturer
(2)
Electronic ID Device
(2)
Read
(3)
Standby
Hardware /RESET
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
(2)
Temporary Sector Unprotect
/CE
L
L
L
H
X
L
L
L
L
X
/OE
L
L
L
X
X
H
H
V
ID
L
X
/WE
H
H
H
X
X
H
L
L
H
X
A0
L
H
A0
X
X
X
A0
X
L
X
A1
L
L
A1
X
X
X
A1
X
H
X
A6
L
L
A6
X
X
X
A6
X
L
X
A9
V
ID
V
ID
A9
X
X
X
A9
V
ID
V
ID
X
DQ0-DQ7 DQ8-DQ15
Code
Code
D
OUT
High Z
High Z
High Z
D
IN(4)
X
Code
X
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
/RESET
H
H
H
H
L
H
H
H
H
V
ID
Notes:
1. L = V
IL
, H = V
IH
, X = Don’t Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.
3. /WE can be V
IL
if /CE is V
IL
, /OE at V
IH
initiates the write operations.
4. Refer to Table 6 for valid D
IN
during a write operation.
4
HY29F200
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
