CONTENTS
DESCRIPTION.....................................................................................................................................................................................5
FEATURES ...........................................................................................................................................................................................5
MG73N/74N/75N FAMILY LISTING............................................................................................................................................6
ARRAY ARCHITECTURE ................................................................................................................................................................7
MG73N/74N/75N CSA LAYOUT METHODOLOGY................................................................................................................8
ELECTRICAL CHARACTERISTICS ...............................................................................................................................................9
MACRO LIBRARY............................................................................................................................................................................12
OKI ADVANCED DESIGN CENTER CAD TOOLS ..................................................................................................................14
DESIGN PROCESS............................................................................................................................................................................15
AUTOMATIC TEST PATTERN GENERATION ........................................................................................................................16
FLOORPLANNING DESIGN FLOW............................................................................................................................................16
IEEE JTAG BOUNDARY SCAN SUPPORT.................................................................................................................................18
PACKAGE OPTIONS.......................................................................................................................................................................19
TQFP, LQFP and QFP Package Menu.....................................................................................................................................19
MG73N/74N/75N
0.22 µm Customer Structure Array
DESCRIPTION
Oki’s 0.22µm Application-Specific Integrated Circuit (ASIC) products are available in Customer Structured
Array (CSA) architectures. The CSA-based MG75N series use a five-layer metal process on 0.22µm drawn
CMOS technology. The MG73N/74N CSA series uses three and four metal layers, respectively.
The 0.22µm families provide significant performance, density, and power improvement over previous 0.25µm
technologies. An innovative 4-transistor cell structure provides 20% less power and 70% more usable gates than
traditional cell designs. The Oki 0.22µm family operates using 2.5-V VDD core with optimized 3-V I/O buffers.
The 3-, 4-, and 5-layer metal MG73N/74N/75N CSA series contains 21 array bases, offering up to 868 I/O pads
and over 9.3M raw gates. These CSA array sizes are designed to fit the most popular quad flat pack (QFP), low
profile QFPs (LQFPs), thin QFPs (TQFPs), and plastic ball grid array (PBGA).
The 3-layer-metal MG73N, 4-layer-metal MG74N and 5-layer-metal MG75N CSA series contains 21 array bases,
offering a wider span of gate and I/O counts. Oki uses the Virage Components memory compiler which provides
high performance, embedded synchronous single- and dual-port RAM macrocells for CSA designs. As such, the
MG73N/74N/75N series is suited to memory-intensive ASICs and high-volume designs where fine-tuning of
package size produces significant cost or real estate savings.
FEATURES
• 0.22µm drawn 3-, 4-, and 5-layer metal CMOS
• Optimized 2.5-V core
• Optimized 3-V I/O
• Optimized 5-V Tolerant I/O
• SOG and CSA architecture availability
• 50-ps typical gate propagation delay (for a 4x
drive inverter gate with a fanout of 2 and 0 mm
of wire, operating at 2.5 V)
• Over 9.3M raw gates and 868 I/O pads using 60µ
staggered I/O
• User-configurable I/O with V
SS
, V
DD
, TTL, 3-
state, and 1- to 24-mA options
• Slew-rate-controlled outputs for low-radiated
noise
• Clock tree cells which reduces the maximum skew
for clock signals
• Gated clock
• Low 0.2µW/MHz/gate power dissipation
• User-configurable single- and dual-port
memories
• Specialized IP cores and macrocells
including 32-bit ARM7TDMI CPU, phase-
locked loop (PLL), and peripheral
component interconnect (PCI) cells
• Floorplanning for front-end simulation,
backend layout controls, and link to
synthesis
• Joint Test Action Group (JTAG) boundary
scan and scan path Automatic Test Pattern
Generation (ATPG)
• Built-In Self Test (BIST) for memory testing
• Support for popular CAE systems including
Cadence, Model Technology, Inc. (MTI),
and Synopsys
Oki Semiconductor
5
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