without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. 0A
11/01/2016
1
IS62WV10248EFALL/BLL
IS65WV10248EFALL/BLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
48-Pin mini BGA (6mm x 8mm), ERR1/2
1
2
3
4
5
6
A
NC
OE#
A0
A1
A2
CS2
A
NC
OE#
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1#
NC
B
NC
NC
A3
A4
CS1#
NC
C
I/O0
NC
A5
A6
NC
I/O4
C
I/O0
NC
A5
A6
NC
I/O4
D
VSS
I/O1
A17
A7
I/O5
VDD
D
VSS
I/O1
A17
A7
I/O5
VDD
E
VDD
I/O2
NC
A16
I/O6
VSS
E
VDD
I/O2
ERR1
A16
I/O6
VSS
F
I/O3
NC
A14
A15
NC
I/O7
F
I/O3
NC
A14
A15
NC
I/O7
G
NC
NC
A12
A13
WE#
NC
G
NC
ERR2
A12
A13
WE#
NC
H
A18
A8
A9
A10
A11
A19
H
A18
A8
A9
A10
A11
A19
PIN DESCRIPTIONS
A0-A19
I/O0-I/O7
CS1#
CS2
OE#
WE#
ERR1
ERR2
NC
V
DD
VSS
Address Inputs
Data Inputs/Outputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Single ERR Correction Signal
Double ERR Detection Signal
No Connection
Power
Ground
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. 0A
11/01/2016
2
IS62WV10248EFALL/BLL
IS65WV10248EFALL/BLL
44-Pin TSOP (Type II)
44-Pin TSOP (Type II)
,ERR1/ERR2
A4
A3
1
2
3
4
44
43
42
41
40
39
38
37
36
A5
A6
A4
A3
A2
A1
A0
CS1#
ERR2
NC
1
2
3
4
44
43
42
41
40
39
38
37
36
A5
A6
A7
OE#
A2
A1
A7
OE#
A0
CS1#
NC
NC
5
6
7
8
9
10
11
CS2
A8
NC
5
6
7
8
9
10
11
CS2
A8
NC
NC
I/O7
I/O6
VSS
VDD
I/O5
I/O4
NC
NC
I/O0
I/O1
NC
I/O7
I/O6
VSS
VDD
I/O5
I/O4
NC
NC
I/O0
I/O1
VDD
VSS
I/O2
I/O3
NC
ERR1
35
34
35
34
VDD
VSS
I/O2
I/O3
NC
NC
12
13
14
15
16
33
32
31
12
13
14
15
16
33
32
31
30
29
28
30
29
28
WE#
A19
A18
17
18
19
20
21
22
A9
A10
A11
WE#
A19
A18
17
18
19
20
21
22
A9
A10
A11
27
26
25
24
23
27
26
25
24
23
A17
A16
A15
A12
A13
A14
A17
A16
A15
A12
A13
A14
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. 0A
11/01/2016
3
IS62WV10248EFALL/BLL
IS65WV10248EFALL/BLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. SRAM has three different modes supported. Each function is described
below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW). The input and output pins (I/O0-7) are
placed in a high impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
ERROR DETECTION AND ERROR CORRECTION
Independent ECC per each byte
-
detect and correct one bit error per byte or detect 2-bit error per byte
Optional ERR1 output signal indicates 1-bit error detection and correction
Optional ERR2 output signal indicates 2-bit error detection.
Controller can use either ERR1 or ERR2 to monitor ECC event. Unused pins (ERR1 or ERR2) can be left
floating.
Better reliability than parity code schemes which can only detect an error but not correct an error
Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)
Status
No Error
1-Bit Error only 1-bit error per byte detected and corrected
2-Bit Error
Non-Read
2-bit error per byte detected
(out of 4 bytes) or Output Disabled
Write operation
ERR1/2 OUTPUT SIGNAL BEHAVIOR
ERR1
0
1
0
High-Z
ERR2
0
0
1
High-Z
DQ pin
Valid Q
Valid Q
In-Valid Q
Valid D
Remark
TRUTH TABLE
Mode
Not Selected
Not Selected
Output Disabled
Write
Read
CS1#
H
X
L
L
L
CS2
X
L
H
H
H
WE#
X
X
H
H
L
OE#
X
X
H
L
X
I/O0-I/O7
High-Z
High-Z
High-Z
DIN
DOUT
VDD Current
ISB2
ISB2
ICC,ICC1
ICC,ICC1
ICC,ICC1
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. 0A
11/01/2016
4
IS62WV10248EFALL/BLL
IS65WV10248EFALL/BLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Vt er m
Terminal Voltage with Respect to GND
V
DD
tStg
I
OUT
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Value
–0.5 to 3.9 (V
DD
+ 0.3V)
–0.3 to 3.9 (V
DD
+ 0.3V)
–65 to +150
20
Unit
V
V
C
mA
V
DD
Related to GND
Storage Temperature
DC Output Current (LOW)
OPERATING RANGE
(1)
Range
Ambient Temperature
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Note:
1.
P
ART
NUMBER
~ALL
S
PEED
(
MAX
)
55 ns
55 ns
55 ns
45ns
VDD(
MIN
)
1.65V
1.65V
1.65V
2.2V
2.2V
2.2V
VDD(
TYP
)
1.8V
1.8V
1.8V
3.0V
3.0V
3.0V
VDD(
MAX
)
2.2V
2.2V
2.2V
3.6V
3.6V
3.6V
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
-40C to +125C
~BLL
45ns
55ns
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE
(1)
Parameter
Input capacitance
DQ capacitance (IO0–IO7)
Symbol
C
IN
C
I/O
Test Condition
T
A
= 25°C, f = 1 MHz, V
DD
= V
DD
(typ)
Max
6
8
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS
(1)
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to pins
Thermal resistance from junction to case
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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