A43L4616A
4M X 16 Bit X 4 Banks Synchronous DRAM
Preliminary
Document Title
4M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
History
Initial issue
Add Test Mode description
Error Correction:
Change Clock Frequency from 133MHz to 100MHz at CL=2
Remove the x8 configuration
Modify DC, AC spec. and add full page mode
Issue Date
April 18, 2008
August 13, 2008
September 14, 2009
February 22, 2010
May 11, 2010
Remark
Preliminary
PRELIMINARY
(May, 2010, Version 0.4)
AMIC Technology, Corp.
A43L4616A
4M X 16 Bit X 4 Banks Synchronous DRAM
Preliminary
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8, FP)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3, 100Mhz @ CL=2
143MHz @ CL=3, 100Mhz @ CL=2
133MHz @ CL=3, 100Mhz @ CL=2
Industrial temperature operation: -40
°
C to +85
°
C for -U
Automotive temperature operation : -40
°
C to +85
°
C for -A
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
64ms refresh period (8K cycle)
54 Pin TSOP (II)
Lead-free product available
All Pb-free (lead-free) product are RoHS compliant
General Description
The A43L4616A is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 X 4,194,304 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
PRELIMINARY
(May, 2010, Version 0.4)
1
AMIC Technology, Corp.
A43L4616A
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A12
Address
Row address : RA0~RA12, Column address: CA0~CA8.
Selects bank to be activated during row address latch time.
BS0, BS1
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
L(U)DQM
Data Input/Output
Mask
Blocks data input when L(U)DQM active.
LDQM corresponds to
DQ
0
~
DQ
7
, UDQM corresponds to DQ
8
~
DQ
15
DQ
0-15
VDD/VSS
VDDQ/VSSQ
NC
Data Input/Output
Power Supply/Ground
Data Output
Power/Ground
No Connection
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V
±
0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
PRELIMINARY
(May, 2010, Version 0.4)
4
AMIC Technology, Corp.
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