74HC4017; 74HCT4017
Rev. 6 — 1 July 2020
Johnson decade counter with 10 decoded outputs
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded outputs
(Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs (CP0 and CP1)
and an overriding asynchronous master reset input (MR). The counter is advanced by either a
LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0
is HIGH. When cascading counters, the Q5-9 output, which is LOW while the counter is in states
5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the
counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and
CP1). Automatic code correction of the counter is provided by an internal circuit: following any
illegal code the counter returns to a proper counting mode within 11 clock pulses. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
2. Features and benefits
•
•
•
•
•
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
•
JESD8C (2.7 V to 3.6 V)
•
JESD7A (2.0 V to 6.0 V)
Input levels:
•
For 74HC4017: CMOS level
•
For 74HCT4017: TTL level
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
Nexperia
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC4017D
74HCT4017D
74HC4017DB
74HC4017PW
74HC4017BQ
74HCT4017BQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SSOP16
TSSOP16
DHVQFN16
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
4. Functional diagram
13
14
15
CP1
CP0
MR
5-STAGE JOHNSON COUNTER
DECODING AND OUTPUT CIRCUITRY
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
2
4
7
10
1
5
6
9
11
Q5-9
12
001aah242
Fig. 1.
Functional diagram
14
13
15
CTRDIV10/DEC
&
CT = 0
3
2
4
7
10
1
5
6
9
11
12
13
14
CP1
CP0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
3
2
4
7
10
1
5
6
9
11
12
0
1
2
3
4
5
6
7
8
9
15
MR
Q7
Q8
Q9
Q5-9
001aah239
CT≥5
001aah240
Fig. 2.
Logic symbol
Fig. 3.
IEC logic symbol
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 1 July 2020
2 / 21
Nexperia
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
CP1
CP0
MR
Q
FF
1
CP Q
RD
D
D
Q
FF
2
CP Q
RD
Q
FF
3
CP Q
RD
D
Q
FF
4
CP Q
RD
D
Q
FF
5
CP Q
RD
D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig. 4.
Logic diagram
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 1 July 2020
3 / 21
Nexperia
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
001aah244
Fig. 5.
Timing diagram
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 1 July 2020
4 / 21
Nexperia
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
5. Pinning information
5.1. Pinning
74HC4017
74HCT4017
terminal 1
index area
Q1
Q0
Q2
16 V
CC
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
9
001aah238
2
3
4
5
6
7
8
GND
Q8
9
GND
(1)
16 V
CC
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
74HC4017
74HCT4017
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
1
2
3
4
5
6
7
8
Q6
Q7
Q3
1
Q5
001aah241
Transparent top view
Q8
Fig. 6.
Pin configuration SOT109-1 (SO16), SOT338-1
(SSOP16) and SOT403-1 (TSSOP16)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 7.
Pin configuration SOT763-1 (DHVQFN16)
5.2. Pin description
Table 2. Pin description
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9
GND
Q5-9
CP1
CP0
MR
V
CC
Pin
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
8
12
13
14
15
16
Description
decoded output
ground (0 V)
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
clock input (LOW-to-HIGH edge-triggered)
master reset input (active HIGH)
supply voltage
74HC_HCT4017
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 1 July 2020
5 / 21
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