74VCX16374 Low Voltage 16-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
October 1997
Revised June 2005
74VCX16374
Low Voltage 16-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and output enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The 74VCX16374 is designed for low voltage (1.2V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74VCX16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.2V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.0 ns max for 3.0V to 3.6V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Static Drive (I
OH
/I
OL
)
r
24 mA @ 3.0V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 300 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX16374G
(Note 2)(Note 3)
74VCX16374MTD
(Note 3)
Package Number
BGA54A
MTD48
Package Descriptions
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2:
Ordering code “G” indicates Trays.
Note 3:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500066
www.fairchildsemi.com
74VCX16374
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names
OE
n
CP
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
No Connect
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
Pin Assignment for FBGA
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
2
4
CP
1
NC
V
CC
GND
GND
GND
V
CC
NC
CP
2
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Tables
Inputs
CP
1
Outputs
I
0
–I
7
H
L
X
X
O
0
–O
7
H
L
O
0
Z
Outputs
I
8
–I
15
H
L
X
X
O
8
–O
15
H
L
O
0
Z
OE
1
L
L
L
H
Inputs
CP
2
L
X
(Top Thru View)
L
X
OE
2
L
L
L
H
H
L
X
Z
O
0
HIGH Voltage Level
LOW Voltage Level
Immaterial (HIGH or LOW, inputs may not float)
High Impedance
Previous O
0
before HIGH-to-LOW of CP
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2
74VCX16374
Functional Description
The 74VCX16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CP
n
) transition. With the Output
Enable (OE
n
) LOW, the contents of the flip-flops are avail-
able at the outputs. When OE
n
is HIGH, the outputs go to
the high impedance state. Operations of the OE
n
input
does not affect the state of the flip-flops.
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74VCX16374
Absolute Maximum Ratings
(Note 4)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs 3-STATED
Outputs Active (Note 5)
DC Input Diode Current (I
IK
) V
I
0V
DC Output Diode Current (I
OK
)
V
O
0V
V
O
!
V
CC
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
Storage Temperature Range (T
STG
)
0.5V to
4.6V
0.5V to
4.6V
0.5V to
4.6V
0.5V to V
CC
0.5V
50 mA
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output in “OFF” State
Output Current in I
OH
/I
OL
V
CC
V
CC
V
CC
V
CC
V
CC
3.0V to 3.6V
2.3V to 2.7V
1.65V to 2.3V
1.4V to 1.6V
1.2V
0V to V
CC
0.0V to 3.6V
1.2V to 3.6V
0.3V to
3.6V
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
t/
'
V)
V
IN
0.8V to 2.0V, V
CC
3.0V
r
24 mA
r
18 mA
r
6 mA
r
2 mA
r
100
P
A
40
q
C to
85
q
C
10 ns/V
Note 4:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
V
IL
LOW Level Input Voltage
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
1.2
V
OH
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
2.0
1.6
0.65 x V
CC
0.65 x V
CC
0.65 x V
CC
0.8
0.7
0.35 x V
CC
0.35 x V
CC
0.05 x V
CC
V
CC
- 0.2
2.2
2.4
2.2
V
CC
- 0.2
2.0
1.8
1.7
V
CC
- 0.2
1.25
V
CC
- 0.2
1.05
V
CC
- 0.2
V
V
V
Min
Max
Units
100
P
A
12 mA
18 mA
24 mA
100
P
A
6 mA
12 mA
18 mA
100
P
A
6 mA
100
P
A
2 mA
100
P
A
2.7 - 3.6
2.7
3.0
3.0
2.3 - 2.7
2.3
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.2
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4
74VCX16374
DC Electrical Characteristics
Symbol
V
OL
Parameter
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
100
P
A
12 mA
18 mA
24 mA
100
P
A
12 mA
18 mA
100
P
A
6 mA
100
P
A
2 mA
100
P
A
2.7 - 3.6
2.7
3.0
3.0
2.3 - 2.7
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.2
1.2 - 3.6
1.2 - 3.6
0
1.2 - 3.6
1.2 - 3.6
2.7 - 3.6
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
0.05
V
Conditions
Min
Max
Units
0
d
V
I
d
3.6V
0
d
V
O
d
3.6V
V
I
V
IH
or V
IL
0
d
(V
I
, V
O
)
d
3.6V
V
I
V
CC
or GND
V
CC
d
(V
I
, V
O
)
d
3.6V (Note 7)
V
IH
V
CC
0.6V
r
5.0
r
10
10
20
P
A
P
A
P
A
P
A
P
A
r
20
750
'
I
CC
Note 7:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock Frequency
C
L
(Note 8)
Conditions
V
CC
(V)
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
T
A
40
q
C to
85
q
C
Max
Min
250
200
100
80
40
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
0.8
1.0
1.5
1.0
1.5
1.5
1.5
2.5
3.0
6
Units
Figure
Number
Figures
1, 2
30 pF, R
L
500
:
ns
Figures
7, 8
3.0
3.9
7.8
15.6
39
3.5
4.6
9.2
18.4
46
3.5
3.8
6.8
13.6
34
ns
Figures
7, 9, 10
Figures
1, 6
ns
Figures
6, 7
Figures
1, 3, 4
ns
Figures
7, 9, 10
Figures
1, 3, 4
ns
Figures
7, 8
Figures
1, 2
C
L
t
PHL
,
t
PLH
C
L
t
PZL
,
t
PZH
C
L
t
PLZ
,
t
PHZ
C
L
t
S
Setup Time
C
L
Output Disable Time
C
L
Output Enable Time
C
L
Propagation Delay CP to O
n
C
L
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
15 pF, R
L
30 pF, R
L
2k
:
500
:
1.5
r
0.1
1.2
3.3
r
0.3
2.5
r
0.2
1.8
r
0.15
C
L
15 pF, R
L
2k
:
1.5
r
0.1
1.2
5
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