• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2400
1
Rev. 1.1, September 19, 2017
MX25L3233F
(J / K Grade)
Contents
1. FEATURES ........................................................................................................................................................ 3
2. GENERAL DESCRIPTION ............................................................................................................................... 4
8. ORDERING INFORMATION ............................................................................................................................ 16
9. PART NAME DESCRIPTION ........................................................................................................................... 17
10. PACKAGE INFORMATION ............................................................................................................................ 18
11. REVISION HISTORY ..................................................................................................................................... 22
P/N: PM2400
2
Rev. 1.1, September 19, 2017
MX25L3233F
(J / K Grade)
32M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
•
33,554,432 x 1 bit structure
or 16,777,216 x 2 bits (two I/O read mode)
structure
or 8,388,608 x 4 bits (four I/O mode) structure
• 1024 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 128 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 64 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 ~ 3.6 volt for read, erase, and program
operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Conform with AEC-Q100
• Fast read for SPI mode
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions
- Configurable dummy cycle number for fast read
operation
• Programming: 256byte page buffer
• Minimum 100,000 erase/program cycles
• 20 years data retention
• Auto Erase and Auto Program Algorithms
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse width (Any page to be programmed
should have page in the erased state first.)
•
Status Register Feature
•
Command Reset
•
Program/Erase Suspend
•
Program/Erase Resume
•
Electronic Identification
- RES command for 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x
I/O mode or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
-
Serial Data Output or Serial Data Input/Output for
2 x I/O mode or Serial Data Input/Output for 4 x I/O
mode
• WP#/SIO2
-
Hardware Write Protection or Serial Data Input/Out-
put for 4 x I/O mode
• HOLD#/SIO3
-
To pause the device without deselecting the device
or Serial Data Input/Output for 4 x I/O mode
• PACKAGE
-
8-pin SOP (150mil)
-
8-pin SOP (200mil)
-
16-SOP (300mil)
-
6x5mm 8-WSON
-
All devices are RoHS Compliant and Halogen-
free
-
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block Lock Protection
The BP0-BP3 and T/B status bits define the site of
the area to be protected against program and erase
instructions.
• Additional 4K bits secured OTP
- Features unique identifier
- Factory locked identifiable and customer lockable
P/N: PM2400
3
Rev. 1.1, September 19, 2017
MX25L3233F
(J / K Grade)
2. GENERAL DESCRIPTION
MX25L3233F is 32Mb bits Serial NOR Flash memory, which is configured as 4,194,304 x 8 internally. When it is
in four I/O mode, the structure becomes 8,388,608 bits x 4. When it is in two I/O mode, the structure becomes
16,777,216 bits x 2.
MX25L3233F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire
bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a
serial data output (SO). Serial access to the device is enabled by CS# input.
MX25L3233F, MXSMIO
®
(Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L3233F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
For detailed electrical specifications, please refer to MX25L3233F datasheet.
P/N: PM2400
4
Rev. 1.1, September 19, 2017
MX25L3233F
(J / K Grade)
3. PIN CONFIGURATION
16-PIN SOP (300mil)
HOLD#/SIO3
VCC
NC
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
4. PIN DESCRIPTION
SYMBOL
DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1xI/O)/ Serial Data
SI/SIO0 Input & Output (for 2xI/O mode and 4xI/O
mode)
Serial Data Output (for 1xI/O)/Serial Data
SO/SIO1 Input & Output (for 2xI/O mode and 4xI/O
mode)
SCLK
Clock Input
Write protection Active Low or Serial Data
WP#/SIO2
Input & Output (for 4xI/O mode)
To pause the device without deselecting
HOLD#/
the device or Serial data Input/Output for
SIO3
4 x I/O mode
VCC
+ 3.0V Power Supply
GND
Ground
NC
No Connection
Note:
1. The pin of HOLD#/SIO3 or WP#/SIO2 will remain
internal pull up function while this pin is not
physically connected in system configuration.
However, the internal pull up function will be disabled
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