HIP9022
PRELIMINARY
Data Sheet
October 1998
File Number 4509.1
Dual High Speed Laser Driver
The HIP9022 Dual High Speed Laser Driver is designed to
operate with a constant current drain from the power supply.
This current defines the laser operating power. The current is
accurately controlled in the range of 0.5A to 2A to deliver
constant optical power from the laser when used with an
external Power FET and Power Sense resistor. The operating
circuit allows flexibility in choosing driver current levels.
Eight S/H circuits are multiplex bus controlled to provide
analog data for the dual laser drivers. The bus is updated
during the blanking period of the laser printer scan with a
data rate up to 2.5MHz. A “thermo-electric-cooler” control
circuit provides temperature control of the laser. Two on-chip
ESD diodes protect each laser.
A principle advantage of the Dual High Speed Laser Driver is
accomplished by managing the high currents externally with
discrete Power FETs and thereby not forcing large switching
currents to exist on the same IC substrate with the precision
control circuitry.
Features
• Dual High Speed Laser Driver with Data Rates up to
2.5MHz
• 0.5A to 2A Range of Constant Current Source Controlled
to 0.1% Full Scale
• Low Signal Transients with Controlled Constant Current
Switching
• Laser Optical Power Controlled to Better than 0.5%
• Thermoelectric Cooler (TEC) Circuit to Control
Temperature to within 0.25
o
C
• Multiplexed Sample/Hold (S/H) Bus Interface
• Serial Diagnostic Bus with Multiplexed Output
• High Current ESD Diodes for Laser Diode Protection
Applications
• Dual Laser Printer Driver
Ordering Information
PART NUMBER
HIP9022AM
TEMP.
RANGE (
o
C)
0 to 100
PACKAGE
68 Ld PLCC
PKG. NO.
N68.95
Pinout
HIP9022 (PLCC)
TOP VIEW
NC
V
DD
ESD LASER PS-1
ESD LASER PS-1
ESD SHUNT DRAIN-1
ESD SHUNT DRAIN-1
ESD SHUNT DRAIN-1
ESD LASER GND
ESD LASER GND
ESD SHUNT DRAIN-2
ESD SHUNT DRAIN-2
ESD SHUNT DRAIN-2
ESD LASER PS-2
ESD LASER PS-2
RLY_IN
RLY_OUT
V9P
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VUP1
SG_1
VLOW1
V
EE
GNDA1
GNDD1
CC1
XTEN1+
XTEN1-
CTC1-10K
CTC1-27K
LASERON1B
OC1
TECFB1
TECREF1
TECGDR1
TRES1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OT1
NC
INVERT
RESETB
DIAGINB
NULLB
SB_H
NC
V
IN
V
CC
A3
A2
A1
A0
DIAG
NC
TECREFR
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VUP2
SG_2
VLOW2
GNDA2
GNDD2
CC2
XTEN2+
XTEN2-
CTC2-10K
CTC2-27K
LASERON2B
OC2
TECFB2
TECREF2
TECGDR2
TRES2
OT2
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
HIP9022
ESD
LASERPS-1
6
7
ESD
SHUNT
DRAIN-1
4
5
3
ESD
LASER
GND GND
2
1
X
ESD
SHUNT
ESD
DRAIN-2
LASERPS-2
65 64
68 67 66
LASER P.S.
3 TO 5V
A6
PD
+12V
8
1µF
V
DD
NC
9
+
V
DD
62
ESDD1
9V REG.
V/I REF.
V9P
A4
61
LD1
LD2
ESDD2
63
RLY_IN
RLY_OUT
V9P
1µF
V
CC
RELAY1
+9V
LASER
-
VUP1 10
SG_1 11
VLOW1 12
-5V
1µF
13
V
EE
GNDA1 14
GNDD1 15
CC1 16
XTEN1+ 17
12kΩ
XTEN1- 18
LASER
GATE
DRIVE
60
VUP2
SG_2
1µF
Q3
59
A3
+
58
A5
-
1µF
57
GNDA2
11kΩ
OTA GATE 11kΩ
DRIVE AMP.
V
CC
+
-
A2
CURRENT
MONITOR
1kΩ AMP.
+
A1
X10
56
RF3V49092
VLOW2
X
I
DL
GNDD2
CC2
55
0.1µF
Q2
THERMAL RELATED COMPONENTS
R
S
0.25Ω
54
XTEN2+
-
53
52
XTEN2-
THERM.
COMP
ON/OFF
CTC2-10K
0.02µF
0.1µF
51
CTC2-27K
CTC2-10K 19
50
CTC1-27K 20
30kΩ
O. C.
COMP.
+
PU
LASER_ON2B
49
OC2
48
TECFB2
47
TECREF2
46
TECGDR2
TRES2
-
21
LASER_ON1B
OC1 22
PU
TECFB1 23
TEC DRIVER
(THERMO
ELECTRIC
COOLER
CIRCUIT)
AND
TEC P.S.
3V
Q1
RFD3055
OR
EQUIV. TEC
TECREF1 24
TECGDR1 25
OVER/UNDER
TEMPERATURE
COMPARATOR
45
44
TRES1 26
1.9V
OT1 27
NC 28
SAMPLE/HOLD
SYSTEM
PD
29
INVERT
PD
30
RESETB
PU
PU
31
DIAGINB
PU
32
NULLB
SB_H
33
34
NC
35
36
37
A3
+5V
PU
38
A2
PU
39
A1
V
TEST
OUT
OT2
(THERMO-RESISTOR
SENSES LASER TEMP.,
NEG. TEMP. COEF.,
TEC COOLS LASER.)
LASER DRIVER-1
LASER DRIVER-2
PU
40
PU
41
42 43
NC
NOTE:
PU = 60kΩ PULLUP RESISTOR
TO V
CC
PD = 60kΩ PULLDOWN RESISTOR
TO GND
= SCHMITT TRIGGER HYSTERESIS
TECREFR
(TEMP. REF.
RESISTOR)
5 - 10kΩ
V
IN
V
CC
A0 DIAG
FIGURE 1. HIGH SPEED LASER DRIVER FUNCTIONAL BLOCK DIAGRAM SHOWN IN QUIESCENT P.S. CURRENT TEST MODE
-
+
4-2
HIP9022
Pin Descriptions
PIN
NUMBER
1, 2
3, 4, 5
6, 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SYMBOL
ESD LASER GND
Laser supply and system ground.
DESCRIPTION
ESD SHUNT DRAIN-1 Laser diode ESD protection.
SD LASER PS-1
V
DD
NC
VUP1
SG_1
VLOW1
V
EE
GNDA1
GNDD1
CC1
XTEN1+
XTEN1-
CTC1-10K
CTC1-27K
LASERON1B
OC1
TECFB1
TECREF1
TECGDR1
TRES1
OT1
NC
INVERT
Laser power supply ESD protection.
Input for 12V power supply.
No connection.
Filter capacitor for internally generated shunt gate upper voltage level (1µF).
Drive output to shunt Power FET gate.
Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1µF).
Input for -5V power supply.
Analog Ground.
Digital Ground.
Gate drive to the current source Power FET.
Times 10 constant current monitor amplifier input from the high side of the sense resistor.
Times 10 constant current monitor amplifier input from the low side of the sense resistor.
Thermal compensation short time constant where T
TC
= External C x 10kΩ. (External C typically equal
0.02µF).
Thermal compensation long time constant where T
TC
= External C x 27kΩ. (External C typically equal
0.1µF).
Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power
FET OFF and the Laser ON. These pins have an internal pull-up.
Laser over-current indicator flag.
Feedback to stabilize the TEC loop.
Feedback to stabilize the TEC loop.
Thermo-Electric Cooler Power FET gate drive.
Thermo-Resistor output to ground connection for TEC control.
Laser out of temperature range indication.
No connection.
High input converts to operation with Pmos Current source and NDmos shunt Power FET external
transistors. Low input converts to operation with NDmos Current source and Pmos high side shunt Power
FET external transistors. This pin has an internal pull-down.
When RESETB is held low, three reset actions occur. The LASERONB input is defeated to a Laser Off con-
dition. The SG_1, 2 outputs are switched to VLOW when in the INVERT low mode and to VUP when in the
INVERT high mode. The TEC amplifier is turned off to switch the TECGDR1, 2 outputs to Ground. This pin
has an internal pull-down.
Low level activates the diagnostic mode. This pin has an internal pull-up.
Auto-zeros the S/H amplifier selected by address when held low. This pin has an internal pull-up.
Samples the selected address when held low. The setup time for address is <25ns. This pin has an internal
pull-up.
No connection.
Analog voltage sampled by selected S/H. The input voltage range is 0 to 5V. There is an internal voltage
clamp for voltage outside of this range. There is an internal 2 - 3µs filter for noise rejection.
Input for 5V power supply.
Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
30
RESETB
31
32
33
34
35
36
37
DIAGINB
NULLB
SB_H
NC
V
IN
V
CC
A3
4-3
HIP9022
Pin Descriptions
PIN
NUMBER
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64, 65
66, 67, 68
(Continued)
DESCRIPTION
Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
Diagnostic output, A 0V - 5V analog signal output limits internally to a range of -0.3V to 5.3V. The output is
the channel addressed by A0 - A3.
No connection.
External resistor to ground with a resistor value equal to the value of the thermo-resistor at the desired laser
temperature. (Typically in the 5kΩ to 10kΩ range)
Laser out of temperature range indication.
Thermo-Resistor output to ground connection for TEC control.
Thermo-Electric Cooler Power FET gate drive.
Feedback to stabilize the TEC loop.
Feedback to stabilize the TEC loop.
Laser over-current indicator flag.
Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power
FET OFF and the Laser ON. These pins have an internal pull-up.
Thermal compensation long time constant where T
TC
= External C x 27kΩ. (External C typically equal
0.1µF).
Thermal compensation short time constant where T
TC
= External C x 10kΩ. (External C typically equal
0.02µF).
Times 10 constant current monitor amplifier input from the low side of the sense resistor.
Times 10 constant current monitor amplifier input from the high side of the sense resistor.
Gate drive to the current source Power FET.
Digital Ground.
Analog Ground.
Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1µF).
Drive output to shunt Power FET gate.
Filter capacitor for internally generated shunt gate upper voltage level (1µF).
Filter capacitor bypass for internally generated 9V power source (1µF).
Relay output drive from an N-channel FET controls an external relay to switch the Laser power supply or
power supply interlock ON/OFF for both Laser Drivers.
Relay input control with 5V CMOS logic. A high switches on the relay. This pin has an internal pulldown.
Laser power supply ESD protection.
SYMBOL
A2
A1
A0
DIAG
NC
TECREFER
OT2
TRES2
TECGDR2
TECREF2
TECFB2
OC2
LASERON2B
CTC2-27K
CTC2-10K
XTEN2-
XTEN2+
CC2
GNDD2
GNDA2
VLOW2
SG_2
VUP2
V9P
RLY_OUT
RLY_IN
ESD LASER PS-2
ESD SHUNT DRAIN-2 Laser diode ESD protection.
4-4
HIP9022
Absolute Maximum Ratings
Maximum Analog Supply Voltage, V
DD
. . . . . . . . . . . -0.3V to 14V
Logic Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Analog Negative Supply Voltage, V
EE
. . . . . . . . . . . . . 0.3V to -5.5
Maximum Laser Protection Diode Current . . . . . . . . . . 10A, 200ns
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JC
(
o
C/W)
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Maximum Operating Junction Temperature, T
J
. . . . . . . . . . . 100
o
C
Maximum Storage Temperature Range, T
STG
. . . . -55
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
Operating Conditions
V
DD
Supply Voltage Range, V
DD
. . . . . . . . . . . . . . 11.4V to 12.6V
V
CC
Supply Voltage Range, V
CC
. . . . . . . . . . . . . . . . 4.5V to 5.5V
V
EE
Supply Voltage Range, V
EE
. . . . . . . . . . . . . . . . -4.5V to -5.5V
Laser Power Supply Range, V
LAS
. . . . . . . . . . . . . . . . . . 3V to 5V
TEC Power Supply Range, V
TEC
. . . . . . . . . . . . . . . . . . . 3V to 5V
Laser Operating Current Range, I
DL
. . . . . . . . . . . . . . . . . 0A to 2A
TEC Operating Current Range, I
TEC
. . . . . . . . . . . . . . . . . 0A to 2A
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . -V
EE
, Substrate
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
J
= 100
ο
C, V
DD
= 12V, V
CC
= 5V, V
EE
= -5V, INVERT Low (Figure 1 Configuration)
Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
POWER SUPPLIES
V9P Voltage, No External Load
V9P Thermal Shutdown
V9P Thermal Shutdown Recovery
V9P Current Limiting
V
DD
Power Supply Current
V
CC
Power Supply Current
V
EE
Power Supply Current
V9P
1µF Tantalum
Capacitor to V9P
-
150
-
65
9
-
-
-
25
1.5
-23
-
-
125
-
75
25
-
V
o
C
o
C
mA
mA
mA
mA
I
DD
I
CC
I
EE
-
-
-75
LOGIC/DIGITAL INPUTS
(A0-A3, NULLB and SB_H, LASERON1B, LASERON2B with 60kΩ Pullup Resistors; INVERT, RESETB, RLY_IN 60kΩ
with Pulldown Resistors)
Low Level Input Voltage
High Level Input Voltage
Minimum Hysteresis
Low Level Input Current (Inputs with Pullups)
High Level Input Current (Inputs with Pulldowns)
CONSTANT CURRENT CONTROLLER
OTA Gate Drive Amp. (A2) Voltage Output Range
Current Monitor Amp. (A1) Gain
Current Monitor Amp. Differential Sense Input Range
Current Monitor Amp. Input Offset
Current Monitor Amp. Common Mode Input Range
SHUNT CURRENT SWITCH CONTROLLER
Shunt Gate Output Rise/Fall time
Propagation Delay, LASERONB1, 2 to SG_1, 2
V
G
A
VS
V
IN
V
IO
V
IC
-4
9.8
0
-5
0
-
10
-
-
-
V
CC
10.2
500
5
5
V
-
mV
mV
V
V
IL
V
IH
V
HYS
I
IL
I
IH
0
3.5
0.3
-140
-
-
-
-
-
-
1.5
V
CC
+ 0.3
-
-
140
V
V
V
µA
µA
(Note 2) V
UPPER
= 2V, V
LOWER
= -1V, Gate Load = 5000pF, VUP1, 2; 1µF Filter Capacitor to
GND, VLOW1, 2; 1µF Filter Capacitor to GND, Unless Otherwise Specified
t
R
/t
F
t
D
10% -90% Rise,
90% -10% Fall
T
J
= 100
o
C
T
J
= -25
o
C
-
-
-
0
-4
-
80
60
-
-
20
110
95
V
CC
V
CC
ns
ns
ns
V
V
Drive Output Voltage
V
UPPER
V
LOWER
4-5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
