HIP7010
ADVANCE INFORMATION
August 1996
J1850 Byte Level Interface Circuit
Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a
member of the Intersil family of low-cost multiplexed wiring
ICs. The integrated functions of the HIP7010 provide the
system designer with components key to building a “Class B”
multiplexed communications network interface, which fully
conforms to the VPW Multiplexed Wiring protocol specified
in the SAE J1850 Standard. The HIP7010 is designed to
interface with a wide variety of Host microcontrollers via a
standard three wire, high-speed (1MHz), synchronous, serial
interface. The HIP7010 automatically produces properly
framed VPW messages,
prepending
the Start of Frame
(SOF) symbol and calculating and appending the CRC
check byte. All circuitry needed to decode incoming mes-
sages, to validate CRC bytes, and to detect Breaks, End of
Data (EOD), Idle bus, and illegal symbols is included. In-
Frame Responses (IFRs) are fully supported for Type 1,
Type 2, and Type 3 messages, with the appropriate Normal-
ization Bit automatically generated. The HCMOS design
allows proper opeSration at various input frequencies from
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-
sil HIP7020.
Features
• Fully Supports VPW (Variable Pulse Width) Messaging
Practices of SAE J1850 Standard for Class B Data
Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI
Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010
Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last
Byte
• Fail-Safe Design Including, Slow Clock Detection
Circuitry, Prevents J1850 Bus Lockup Due to System
Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol
(Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of
Normalization Bits (NB) for Type 1, Type 2, and Type 3
Messages
• Wait-For-Idle Mode Reduces Host Overhead During
Non-Applicable Messages
• Status Register Flags Provide Information on Current
Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus
Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for
In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and
Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40
o
C to +125
o
C Operating Range
• Single 3.0V to 6.0V Supply
Ordering Information
TEMP.
PART NUMBER RANGE (
o
C)
HIP7010P
HIP7010B
-40 +125
-40 +125
PACKAGE
14 Lead Plastic DIP
14 Lead Plastic SOIC (N)
PKG. NO.
E14.3
M14.15
Pinout
HIP7010 (SOIC, PDIP)
TOP VIEW
IDLE 1
VPWIN 2
VPWOUT 3
V
DD
4
RESET 5
TEST 6
SACTIVE 7
14 RDY
13 STAT
12 CLK
11 V
SS
10 SIN
9 SOUT
8 SCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
3644.2
1
HIP7010
Block Diagram
SIN
10
A
B MUX
C
LSB
MSB
OUTPUT DATA
3
VPWOUT
J1850 VPW SYMBOL
ENCODER/DECODER
DATA SHIFT REGISTER
DECODED VPW IN
2
VPWIN
9
SOUT
A
MUX
B
STATUS/CONTROL BYTE
CRC GENERATOR/CHECKER
SCK
IDLE
RDY
STAT
CLK
RESET
TEST
SACTIVE
8
1
14
13
12
5
6
7
TIMING
GENERATOR
STATE MACHINE
AND CONTROL LOGIC
V
DD
4
V
SS
11
Pin Description
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN NAME
IDLE
VPWIN
VPWOUT
V
DD
RESET
TEST
SACTIVE
SCK
SOUT
SIN
V
SS
CLK
STAT
RDY
IN/OUT
OUT
IN
OUT
-
IN
IN
OUT
OUT
OUT
IN
-
IN
IN
IN
CMOS Output
CMOS Schmitt (No V
DD
Diode)
CMOS Output
Power Supply
CMOS Schmitt (No V
DD
Diode)
CMOS Input with Pull-Down
CMOS Output
Three-State with Pull-Down
Three-State with Pull-Down
CMOS Input with Pull-Down
Ground
CMOS Schmitt (No V
DD
Diode)
CMOS Input with Pull-Down
CMOS Input with Pull-Down
PIN DESCRIPTION
2
HIP7010
Absolute Maximum Ratings
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +7.0V
Input or Output Voltage
Pins with V
DD
Diode . . . . . . . . . . . . . . . . . . . .-0.3V to V
DD
+0.3V
Pins without V
DD
Diode . . . . . . . . . . . . . . . . . . . . -0.3V to +10.0V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2500 Gates
Thermal Information
Thermal Resistance
θ
JA
Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . .+100
o
C/W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+120
o
C/W
Maximum Package Power Dissipation at +125
o
C
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250mW
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mW
Operating Temperature Range (T
A
) . . . . . . . . . . . -40
o
C to +125
o
C
Storage Temperature Range (T
STG
). . . . . . . . . . . -65
o
C to +150
o
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
o
C
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -40
o
C to +125
o
C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .(0.8V
DD
) to V
DD
Input Rise and Fall Time
CMOS Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ns Max
CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited
Electrical Specifications
Supply Current
Operating Current
Power-Down Mode (Note 1)
Clock Stopped (Note 2)
Input High Voltage
T
A
= -40
o
C to +125
o
C, V
DD
= 5V
DC
±10%,
Unless Otherwise Specified
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETERS
I
OP
I
PD
I
STOP
CLK = 2.0 MHz
PD = 1
CLK = V
SS
or V
DD
-
-
-
1.0
50
5.0
5.0
150
50
mA
µA
µA
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
Input Low Voltage
CMOS Level (SIN, STAT, RDY, TEST)
Schmitt Trigger (RESET, CLK, VPWIN)
High Level Input Current
(CLK, VPWIN, RESET)
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
Low Level Input Current
(CLK, VPWIN, RESET)
Input Buffer with Pull-Down (SIN, TEST, STAT, RDY)
Output High Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
Output Low Voltage
(SCK, SOUT, VPWOUT, IDLE, SACTIVE)
High Impedance Leakage Current
Three-State with Pull-Down (SCK, SOUT)
V
IH
0.7V
DD
0.8V
DD
-
-
V
DD
V
DD
V
V
V
IL
V
SS
V
SS
-
-
0.3V
DD
0.2V
DD
V
V
I
IH
V
IN
= V
DD
-1
100
0.001
200
1
500
µA
µA
µA
µA
I
IL
V
IN
= V
SS
-1
-10
-0.001
-0.01
1
10
V
OH
I
LOAD
= 0.8 mA
V
DD
-0.8
-
-
V
V
OL
I
LOAD
= -1.6 mA
-
-
0.4
V
I
OZ
V
OUT
= V
DD
V
OUT
= V
SS
100
-10
0.2
200
500
10
µA
µA
V
Schmitt Trigger Hysteresis Voltage
(RESET, CLK, VPWIN)
NOTES:
V
HYS
0.5
2.0
1. SIN, STAT, RDY, and TEST = V
SS
;
SACTIVE, SCK, and SOUT unconnected;
VPWIN = V
DD
; CLK = 10MHz.
2. SIN, STAT, RDY, and TEST = V
SS
;
SACTIVE, SCK, and SOUT unconnected; VPWIN = V
DD
; PD = 1.
3
HIP7010
Serial Interface Timing
NUMBER
-
-
(1)
(2)
SYMBOL
-
-
t
CYC
t
LEAD
Operating Frequency
Input CLK Duty Cycle
SCK Cycle Time
SACTIVE Lead Time
Before Status/Control Transfer
Before Data Transfer
(3)
t
LAG
SACTIVE Lag Time
After Status/Control Transfer
After Data Transfer
(4)
(5)
(6)
(7)
(8)
(9)
t
SCKH
t
SCKL
t
DVSCK
t
SCKDX
t
DZDA
t
DADZ
t
DVSCK
t
DXSCK
t
RISE
t
FALL
t
STATH
t
RDYH
t
RESETL
(16)
t
SACTIVE
Clock (SCK) HIGH Time
Clock (SCK) LOW Time
Required Data In Setup Time (SIN to SCK)
Required Data In Hold Time (SIN after SCK)
Data Active from High Impedance Delay (SACTIVE to SOUT Active)
Data Active to High Impedance Delay (SACTIVE to SOUT High
Impedance)
Data Out Setup Time (SOUT
to SCK)
Data Out Hold Time (SOUT after SCK)
Output Rise Time (0.3V
DD
to 0.7V
DD
, C
L
= 100pF)
Output Fall Time (0.7V
DD
to 0.3V
DD
, C
L
= 100pF)
Required STAT Pulse Width
Required RDY Pulse Width
Required RESET Pulse Width
SACTIVE Delay from RDY (IDLE = V
SS
)
SACTIVE Delay from STAT (FTU = 0)
(17)
(18)
(19)
t
RDYSCK
t
SCKRDY
t
REC
f
SLOW
NOTE:
1. All parameters are specifications of the HIP7010 component not of a system. Parameters specified as “Required” (i.e., t
STATH
) refer to
the requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum width
that any HIP7010 device will require. Therefore, a system that provides a
minimum
pulse width of 75ns will satisfy this
maximum
requirement.
Required RDY Removal Time Prior to Last SCK for Short RDY
Required RDY Hold Time after Last SCK for Long RDY
Required SERIAL Recovery Time (Minimum Time after SACTIVE
Until Next RDY/STAT)
Slow clock detect frequency limit
650
1250
450
450
-
-
-10
-
750
1300
500
500
10
-10
10
10
850
1400
550
550
50
40
-
40
ns
ns
ns
ns
ns
ns
ns
ns
450
1150
750
1225
850
1300
ns
ns
(See Figure 1- Figure 7) T
A
= -40
o
C to +125
o
C, V
DD
= 5V
DC
±10%,
Unless Otherwise Specified
PARAMETERS
MIN
2
40
-
TYP
8
50
1.0
MAX
12
60
-
UNITS
MHz
%
MHz
(10)
(11)
(12)
(13)
(14)
(15)
375
375
15
7
-
-
-
1150
5
-
-
-
475
475
75
25
20
20
20
1750
285
25
0
675
-
-
150
75
75
75
75
2450
900
100
100
750
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
80
200
KHz
4
HIP7010
STAT
(INPUT)
(14)
RDY (SHORT)
(INPUT)
(15)
RDY (LONG)
(INPUT)
SACTIVE
(OUTPUT)
(16)
(17)
(18)
(19)
(2)
(1)
(13)
(12)
(3)
SCK
(OUTPUT)
(4)
(5)
D7O
D6O
D0O
(9)
SOUT
(OUTPUT)
(8)
(10)
(11)
D7I
D6I
D0I
SIN
(INPUT)
(6)
(7)
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM
NOTES:
1. Measurement points are from V
DD
/2, except 12 and 13 which are measured between V
IL
and V
IH.
2. All timings assume proper CLK frequency and Divide Select values to generate 1MHz SCK.
Functional Pin Description
This section provides a description of each of the 14 pins of
the HIP7010 as shown in Figure 2.
IDLE 1
VPWIN 2
VPWOUT 3
V
DD
4
RESET 5
TEST 6
SACTIVE 7
14 RDY
13 STAT
12 CLK
11 V
SS
10 SIN
9 SOUT
8 SCK
CLK (Clock - Input)
The Clock input (CLK) provides the basic time base refer-
ence for all J1850 symbol detection and generation. Serial
Bus transfers between the HIP7010 and the Host microcon-
troller are also timed based on the Clock input. Proper VPW
symbol detection and generation requires a 2MHz clock
which is internally derived from the CLK input. Various CLK
input frequencies can be accommodated via the Divide
Select bits in the Status/Control Register (see
Status/Con-
trol Register
for details).
An internal Slow Clock Detect circuit monitors the CLK input
signal and generates a HIP7010 reset if the clock is inactive
for more than
1/f
SLOW
. This is a safety mechanism to prevent
blocking the J1850 and Serial busses in the event of a clock
failure. The Slow Clock Detect reset can also be intentionally
invoked by externally inhibiting CLK input transitions.
Power can be reduced under Host control via the PowerDown
bit in the Status/Control Register (see Status/Control Regis-
ter for details). Setting the Power-Down bit effectively stops
internal clocking of the HIP7010.
FIGURE 2. 14 PIN DIP AND SO TERMINAL ASSIGNMENTS
V
DD
and V
SS
(Power)
Power is supplied to the HIP7010 using these two pins. V
DD
is connected to the positive supply and V
SS
is connected to
the negative supply.
5
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
