I GNS
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S
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DF EP
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14B)
M M E B S TI TU T nd I S L6 6
CO
Data
T RE IBLE SU 614A, a
Sheet
NO
S
L6
POS 6014, IS
(ISL6
®
HIP6602
August 2000
FN4838.1
Dual Channel Synchronous-Rectified
Buck MOSFET Driver
The HIP6602 is a high frequency, two power channel
MOSFET driver specifically designed to drive four power
N-Channel MOSFETs in a synchronous-rectified buck
converter topology. These drivers combined with a HIP63xx
series of Multi-Phase Buck PWM controller and Intersil’s
UltraFETs® form a complete core voltage regulator solution
for advanced microprocessors.
The HIP6602 drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage flexibility provides the
advantage of optimizing applications involving trade-offs
between switching losses and conduction losses.
The output drivers in the HIP6602 have the capacity to
efficiently switch power MOSFETs at high frequencies. Each
driver is capable of driving a 3000pF load with a 30ns
propagation delay and 50ns transition time. This device
implements bootstrapping on the upper gates with only a
single external capacitor required for each power channel.
This reduces implementation complexity and allows the use
of higher performance, cost effective, N-Channel MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
Features
• Drives Four N-channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Under-Voltage Protection
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
Athlon
TM
Microprocessors.
• High Frequency Low Profile DC/DC Converters
• High Current Low Voltage DC/DC Converters
Pinout
HIP6602CB
(SOIC)
TOP VIEW
PWM1
PWM2
GND
1
2
3
14 VCC
13 PHASE1
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
8 PHASE2
Ordering Information
PART NUMBER
HIP6602CB
HIP6602CB-T
TEMP. RANGE
(°C)
0 to 85
PACKAGE
14 Ld SOIC
PKG. NO.
M14.15
14 Ld SOIC Tape and Reel
LGATE1 4
PVCC
PGND
LGATE2
5
6
7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright
©
Intersil Corporation 2000, 2005
Pentium
®
is a registered trademark of Intel Corporation.; AMD
®
is a registered trademark of Advanced Micro Devices, Inc.
UltraFET® is a registered trademark of Intersil Corporation. Athlon™ is a trademark of Advanced Micro Devices, Inc.
HIP6602
Block Diagram
PVCC
BOOT1
UGATE1
VCC
+5V
SHOOT-
THROUGH
PROTECTION
PHASE1
10K
PWM1
PVCC
10K
LGATE1
PGND
+5V
CONTROL
LOGIC
PVCC
PGND
BOOT2
UGATE2
10K
PWM2
10K
GND
SHOOT-
THROUGH
PROTECTION
PHASE2
PVCC
HIP6602
PGND
LGATE2
Typical Application - 2 Channel Converter Using a HIP6302 and a HIP6602 Gate Driver
+5V
+12V
BOOT1
+12V
FB
VSEN
UGATE1
VCC
V
CC
ISEN1
PGOOD
PWM1
MAIN
CONTROL
HIP6302
PWM1
DUAL
DRIVER
HIP6602
LGATE1
+V
CORE
+5V/12V
PHASE1
COMP
PVCC
VID
BOOT2
+12V
PWM2
ISEN2
PWM2
UGATE2
PHASE2
LGATE2
FS/DIS
GND
GND
PGND
2
HIP6602
Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602 Gate Driver
+12V
BOOT1
+12V
UGATE1
VCC
PHASE1
LGATE1
+5V
DUAL
DRIVER
HIP6602
FB
VSEN
COMP
V
CC
PVCC
+5V/12V
BOOT2
+12V
UGATE2
ISEN1
PGOOD
EN
PWM1
PWM2
PWM1
PWM2
LGATE2
PHASE2
VID
MAIN
CONTROL
HIP6303
ISEN2
GND
PGND
+V
CORE
ISEN3
FS/DIS
PWM3
PWM4
GND
ISEN4
UGATE3
VCC
PHASE3
+12V
BOOT3
+12V
LGATE3
DUAL
DRIVER
HIP6602
PVCC
+5V/12V
BOOT4
+12V
UGATE4
PWM3
PWM4
LGATE4
PHASE4
GND
PGND
3
HIP6602
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V
Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V
BOOT Voltage (V
BOOT
- V
PHASE
) . . . . . . . . . . . . . . . . . . . . . . .15V
Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V
UGATE. . . . . . . . . . . . . . . . . . . . . . V
PHASE
- 0.3V to V
BOOT
+ 0.3V
LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
PVCC
+ 0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Thermal Information
Thermal Resistance (Note 1)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
±10%
Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
Power Supply Current
POWER-ON RESET
VCC Rising Threshold
VCC Falling Threshold
PWM INPUT
Input Current
PWM Rising Threshold
PWM Falling Threshold
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
Recommended Operating Conditions, Unless Otherwise Noted
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VCC
I
PVCC
f
PWM
= 500kHz, V
PVCC
= 12V
f
PWM
= 500kHz, V
PVCC
= 12V
-
-
3.7
2.0
5.0
4.0
mA
mA
9.7
9.0
9.95
9.2
10.4
9.5
V
V
µA
V
V
ns
ns
ns
ns
ns
ns
V
ns
Ω
Ω
Ω
Ω
mA
mA
Ω
I
PWM
V
PWM
= 0 or 5V (See Block Diagram)
V
PVCC
= 12V
V
PVCC
= 12V
-
3.45
-
-
-
-
-
-
-
1.4
-
500
3.6
1.45
20
50
20
20
30
20
-
230
-
-
1.55
-
-
-
-
-
-
3.6
-
TR
UGATE
TR
LGATE
TF
UGATE
TF
LGATE
V
PVCC
= V
VCC
= 12V, 3nF Load
V
PVCC
= V
VCC
= 12V, 3nF Load
V
PVCC
= V
VCC
= 12V, 3nF Load
V
PVCC
= V
VCC
= 12V, 3nF Load
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
Shutdown Window
Shutdown Holdoff Time
OUTPUT
Upper Drive Source Impedance
TPDL
UGATE
V
PVCC
= V
VCC
= 12V, 3nF Load
TPDL
LGATE
V
PVCC
= V
VCC
= 12V, 3nF Load
R
UGATE
R
UGATE
I
LGATE
R
LGATE
V
VCC
= 12V, V
PVCC
= 5V
V
VCC
= V
PVCC
= 12V
V
VCC
= 12V, V
PVCC
= 5V
V
VCC
= V
PVCC
= 12V
V
VCC
= 12V, V
PVCC
= 5V
V
VCC
= V
PVCC
= 12V
V
VCC
= 12V, V
PVCC
= 5V or 12V
-
-
-
-
400
500
-
1.7
3.0
2.3
1.1
580
730
1.6
3.0
5.0
4.0
2.0
-
-
4.0
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Sink Impedance
4
HIP6602
Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
PHASE pin. The bootstrap capacitor provides the charge to
turn on the upper MOSFETs. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
VCC (Pin 14)
Connect this pin to a +12V bias supply. Place a high quality
bypass capacitor from this pin to GND. To prevent forward
biasing an internal diode, this pin should be more positive
then PVCC during converter start-up.
GND (Pin 3)
Bias and reference ground. All signals are referenced to this
node.
LGATE1 (Pin 4) and LGATE2 (Pin 7)
Lower gate drive outputs. Connect to gates of the low-side
power N-Channel MOSFETs.
Description
Operation
Designed for versatility and speed, the HIP6602 two channel,
dual MOSFET driver controls both high-side and low-side
N-Channel FETs from two externally provided PWM signals.
The upper and lower gates are held low until the driver is
initialized. Once the VCC voltage surpasses the VCC Rising
Threshold (See Electrical Specifications), the PWM signal
takes control of gate transitions. A rising edge on PWM
initiates the turn-off of the lower MOSFET (see Timing
Diagram). After a short propagation delay [TPDL
LGATE
], the
lower gate begins to fall. Typical fall times [TF
LGATE
] are
provided in the Electrical Specifications section. Adaptive
shoot-through circuitry monitors the LGATE voltage and
determines the upper gate delay time [TPDH
UGATE
] based
on how quickly the LGATE voltage drops below 1.0V. This
prevents both the lower and upper MOSFETs from
conducting simultaneously or shoot-through. Once this delay
period is complete the upper gate drive begins to rise
[TR
UGATE
] and the upper MOSFET turns on.
PVCC (Pin 5)
This pin supplies the upper and lower gate drivers bias.
Connect this pin from +12V down to +5V.
PGND (Pin 6)
This pin is the power ground return for the lower gate
drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13)
Connect these pins to the source of the upper MOSFETs
and the drain of the lower MOSFETs. The PHASE voltage is
monitored for adaptive shoot-through protection. These pins
also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12)
Upper gate drive outputs. Connect to gate of high-side
power N-Channel MOSFETs.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11)
Floating bootstrap supply pins for the upper gate drivers.
Connect the bootstrap capacitor between these pins and the
Timing Diagram
PWM
TPDH
UGATE
TPDL
UGATE
TR
UGATE
TF
UGATE
UGATE
LGATE
TF
LGATE
TPDL
LGATE
TPDH
LGATE
TR
LGATE
5
NXP MCU
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