HIP6500B
TM
Data Sheet
May 2000
File Number
4870
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6500B complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the
3.3V
DUAL
voltage plane from the ATX supply’s 5VSB output,
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output for operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power. A third controller powers up the 5V
DUAL
plane by
switching in the ATX 5V output in active states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins, S3 and S5. Further control of the logic governing
activation of different power states is offered through two
configuration pins, EN3VDL and EN5VDL. In active state, the
3.3V
DUAL
linear regulator uses an external N-Channel pass
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses. In sleep state, power delivery on the 3.3V
DUAL
output is
transferred to an NPN transistor, also external to the controller.
Active state power delivery for the 2.5/3.3V
MEM
output is
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internal pass transistor. The 5V
DUAL
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3V
DUAL
output, the operation of the
5V
DUAL
output is dictated not only by the status of the S3 and
S5 pins, but that of the EN5VDL pin as well. The 3.3V
SB
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5V
CLK
output is only active during S0 and S1,
and uses the 3V3 pin as input source for its internal pass
element.
Features
• Provides 5 ACPI-Controlled Voltages
- 5V Active/Sleep (5V
DUAL
)
- 3.3V Active/Sleep (3.3V
DUAL
)
- 2.5V/3.3V Active/Sleep (2.5/3.3V
MEM
)
- 3.3V Always Present (3.3V
SB
)
- 2.5V Clock (Active Only) (2.5V
CLK
)
• Excellent Output Voltage Regulation
- 3.3V
DUAL
Output:
±2%
Over Temperature; Sleep State
Only
- 2.5V/3.3V
MEM
Output:
±2%
Over Temperature; Both
Operational States (3.3V setting in sleep only)
- 2.5V
CLK
and 3.3V
SB
Output:
±2%
Over Temperature
• Small Size
- Very Low External Component Count
• Selectable Memory Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant
Computers
Pinout
HIP6500B
(SOIC)
TOP VIEW
20 EN3VDL
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
VSEN2
1
5VSB 2
3V3SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL
S3
8
9
S5 10
Ordering Information
PART NUMBER
HIP6500BCB
HIP6500BEVAL1
TEMP.
RANGE (
o
C)
0 to 70
PACKAGE
20 Ld SOIC
PKG.
NO.
M20.3
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
HIP6500B
Absolute Maximum Ratings
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V
12V
+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, V
5VSB
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
±
5%
Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V
Digital Inputs, V
SX
, V
EN5VDL
, V
EN3VDL
. . . . . . . . . . . . . 0 to +5.5V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Shutdown Supply Current
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
5VSB
I
5VSB(OFF)
V
SS
= 0.8V
-
-
30
14
-
-
mA
mA
POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS
Rising 5VSB POR Threshold
5VSB POR Hysteresis
Rising 12V Threshold
12V Hysteresis
Rising 3V3 and 5V Thresholds
3V3 and 5V Hysteresis
Soft-Start Current
Shutdown Voltage Threshold
3.3V
SB
LINEAR REGULATOR (V
OUT1
)
Regulation
3V3SB Nominal Voltage Level
3V3SB Undervoltage Rising Threshold
3V3SB Undervoltage Hysteresis
3V3SB Output Current
2.5/3.3V
MEM
LINEAR REGULATOR (V
OUT2
)
Regulation (Note 2)
VSEN2 Nominal Voltage Level
VSEN2 Nominal Voltage Level
VSEN2 Undervoltage Rising Threshold
VSEN2 Undervoltage Hysteresis (Note 3)
VSEN2 Output Current
I
VSEN2
5VSB = 5V
V
VSEN2
V
VSEN2
R
SEL
= 1kΩ
R
SEL
= 10kΩ
-
-
-
-
-
250
-
2.5
3.3
83
3
300
2.0
-
-
-
-
-
%
V
V
%
%
mA
I
3V3SB
5VSB = 5V
V
3V3SB
-
-
-
-
250
-
3.3
2.739
99
300
2.0
-
-
-
-
%
V
V
mV
mA
I
SS
V
SD
-
-
-
-
-
-
-
-
-
1.0
-
1.0
90
5
10
-
4.5
-
10.8
-
-
-
-
0.8
V
V
V
V
%
%
µA
V
4
HIP6500B
Electrical Specifications
PARAMETER
DRV2 Output Drive Current
DRV2 Output Impedance
3.3V
DUAL
LINEAR REGULATOR (V
OUT3
)
Sleep State Regulation
3V3DL Nominal Voltage Level
3V3DL Undervoltage Rising Threshold
3V3DL Undervoltage Hysteresis
3V3DLSB Output Drive Current
DLA Output Impedance
2.5V
CLK
LINEAR REGULATOR (V
OUT4
)
Regulation
VCLK Nominal Voltage Level
VCLK Undervoltage Rising Threshold
VCLK Undervoltage Hysteresis
VCLK Output Current (Note 4)
5VDUAL SWITCH CONTROLLER (V
OUT5
)
5VDL Undervoltage Rising Threshold
5VDL Undervoltage Hysteresis
5VDLSB Output Drive Current
5VDLSB Pull-up Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past Input UV
Thresholds (Note 5)
Active-to-Sleep Control Input Delay
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT/MSEL)
High Level Input Threshold
Low Level Input Threshold
S3, S5 Internal Pull-Up Impedance to 5VSB
FAULT Output Impedance
TEMPERATURE MONITOR
Fault-Level Threshold (Note 6)
Shutdown-Level Threshold (Note 6)
NOTES:
2. Sleep state only f9or 3.3V setting
3. Valid for 3.3V setting only.
4. At ambient temperatures less than 50
o
C.
5. Guaranteed by correlation.
6. Guaranteed by design.
125
-
-
155
-
-
o
C
o
C
Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3
(Continued)
SYMBOL
I
DRV2
TEST CONDITIONS
5VSB = 5V, R
SEL
= 1kΩ
R
SEL
= 10kΩ
MIN
220
-
TYP
-
200
MAX
-
-
UNITS
mA
Ω
-
V
3V3DL
-
-
-
I
3V3DLSB
5VSB = 5V
5
-
-
3.3
2.739
99
10
90
2.0
-
-
-
-
-
%
V
V
mV
mA
Ω
-
V
VCLK
-
-
-
I
VCLK
V
3V3
= 3.3V
500
-
2.5
2.075
75
800
2.0
-
-
-
-
%
V
V
mV
mA
-
-
I
5VDLSB
5VDLSB = 4V, 5VSB = 5V
-20
-
4.150
150
-
350
-
-
-40
-
V
mV
mA
Ω
20
-
25
200
30
-
ms
µs
-
0.8
-
FAULT = high
-
-
-
50
100
2.2
-
-
-
V
V
kΩ
Ω
5
stm32/stm8
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