HIP6304
TM
Data Sheet
March 2000
File Number
4840
Microprocessor CORE Voltage Regulator
Multi-Phase Buck PWM Controller
The HIP6304 multi-phase PWM control IC together with its
companion gate drivers, the HIP6601, HIP6602 or HIP6603
and Intersil MOSFETs provides a precision voltage
regulation system for advanced microprocessors.
Multiphase power conversion is a marked departure from
earlier single phase converter configurations previously
employed to satisfy the ever increasing current demands of
modern microprocessors. Multi-phase convertors, by
distributing the power and load current results in smaller and
lower cost transistors with fewer input and output capacitors.
These reductions accrue from the higher effective
conversion frequency with higher frequency ripple current
due to the phase interleaving process of this topology. For
example, a two phase convertor operating at 350kHz will
have a ripple frequency of 700kHz. Moreover, greater
convertor bandwidth of this design results in faster response
to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.30V to 2.05V with a system accuracy of
±1%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors. In addition “droop” compensation,
used to reduce the overshoot or undershoot of the CORE
voltage, is easily programmed with a single resistor.
Another feature of this controller IC is the PGOOD monitor
circuit which is held low until the CORE voltage increases,
during its Soft-Start sequence, to within 10% of the
programmed voltage. Over-voltage, 15% above programmed
CORE voltage, results in the converter shutting down and
turning the lower MOSFETs ON to clamp and protect the
microprocessor. Under voltage is also detected and results
in PGOOD low if the CORE voltage falls 10% below the
programmed level. Over-current protection reduces the
regulator current to less than 25% of the programmed trip
value. These features provide monitoring and protection for
the microprocessor and power system.
Features
• AMD Athlon Compatible Multi-Phase Power Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses r
DS(ON)
• Precision CORE Voltage Regulation
-
±1%
System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- 4-Bit VID Input
- 1.30V to 2.05V in 50mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency, (Channel Frequency) Times
Number Channels . . . . . . . . . . . . . . . . . 100kHz to 3MHz
Ordering Information
PART NUMBER
HIP6304CB
HIP6304CB-T
HIP6304EVAL1
TEMP. (
o
C)
0 to 70
PACKAGE
16 Ld SOIC
PKG. NO.
M16.15
16 Ld SOIC Tape and Reel
Evaluation Platform
Pinout
HIP6304 (SOIC)
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
EN 5
COMP 6
FB 7
FS/DIS 8
16 V
CC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Athlon™ is a trademark of Advanced Micro Devices, Inc.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
HIP6304
Block Diagram
PGOOD
V
CC
VSEN
X 0.9
+
UV
OV
LATCH
S
OVP
POWER-ON
RESET (POR)
THREE
STATE
CLOCK AND
SAWTOOTH
GENERATOR
-
FS/EN
+
X1.15
-
+
EN
SOFT-
START
AND FAULT
LOGIC
∑
-
+
-
PWM
PWM1
COMP
VID0
VID1
D/A
VID2
VID3
+
E/A
+
∑
-
+
-
PWM
PWM2
-
FB
CURRENT
CORRECTION
I_TOT
+
OC
∑
-
+
ISEN1
ISEN2
+
I_TRIP
GND
Simplified Power System Diagram
VSEN
PWM 1
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
HIP6304
PWM 2
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
MICROPROCESSOR
VID
2
HIP6304
Typical Application - Two Phase Converter Using HIP6601 Gate Drivers
+12V
PVCC
VCC
BOOT
UGATE
PHASE
V
IN
= +5V
+5V
PWM
DRIVER
HIP6601
LGATE
GND
FB
VSEN
PGOOD
EN
VID3
VID2
VID1
VID0
FS/DIS
GND
COMP
V
CC
PWM2
ISEN2
PVCC
UGATE
VCC
+V
CORE
+12V
BOOT
V
IN
= +5V
MAIN
CONTROL
HIP6304
PWM1
PHASE
PWM
DRIVER
HIP6601
LGATE
GND
ISEN1
Typical Application - Two Phase Converter Using a HIP6602 Gate Driver
+5V
+12V
BOOT1
V
IN
= +12V
FB
VSEN
COMP
VCC
V
CC
ISEN1
UGATE1
PHASE1
PGOOD
EN
VID3
VID2
VID1
VID0
PWM1
PWM1
LGATE1
MAIN
CONTROL
HIP6304
DUAL
DRIVER
HIP6602
PVCC
+V
CORE
+5V
V
IN
+12V
BOOT2
PWM2
ISEN2
PWM2
UGATE2
PHASE2
FS/DIS
GND
GND
LGATE2
PGND
3
HIP6304
R
IN
V
IN
FB
ERROR
AMPLIFIER
HIP6304
COMPARATOR
CORRECTION
+
Q1
PWM
CIRCUIT
PWM1
HIP6601
I
L1
Q2
PROGRAMMABLE
REFERENCE
DAC
L
01
-
+
-
+
∑
-
∑
-
+
CURRENT
SENSING
PHASE
I
SEN1
R
ISEN1
I AVERAGE
CURRENT
AVERAGING
CURRENT
SENSING
I
SEN2
R
ISEN2
V
IN
Q3
PWM
CIRCUIT
PWM2
HIP6601
I
L2
Q4
PHASE
L
02
V
CORE
C
OUT
R
LOAD
-
∑
+
+
-
COMPARATOR
+
∑
CORRECTION
-
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE HIP6304 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER
CHANNEL REGULATOR
Functional Pin Description
VID3 1
VID2 2
VID1 3
VID0 4
EN 5
COMP 6
FB 7
FS/DIS 8
16 V
CC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
FS/DIS (Pin 8)
Channel frequency, F
SW
, select and disable. A resistor from
this pin to ground sets the switching frequency of the
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
VSEN (Pin 10)
Power good monitor input. Connect to the microprocessor-
CORE voltage.
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3) and VID0
(Pin 4)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The HIP6304 decodes
VID bits to establish the output voltage. See Table 1.
ISEN2 (Pin 11) and ISEN1 (Pin 14)
Current sense inputs from the individual converter channel’s
phase nodes.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver.
EN (Pin 5)
Enable pin normal operation is with input open or high. A low
input disables the regulator and three states the PWM outputs.
PGOOD (Pin 15)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
FB (Pin 7)
Inverting input of the internal error amplifier.
4
V
CC
(Pin 16)
Bias supply. Connect this pin to a 5V supply.
HIP6304
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to V
CC
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V
±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
INPUT SUPPLY POWER
Input Supply Current
POR (Power-On Reset) Threshold
Operating Conditions: V
CC
= 5V, T
A
= 0
o
C to 70
o
C, Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
R
T
= 100kΩ, Active and Disabled Maximum Limit
V
CC
Rising
V
CC
Falling
-
4.25
3.75
10
4.38
3.88
15
4.5
4.00
mA
V
V
REFERENCE AND DAC
System Accuracy
DAC (VID0 - VID3) Input Low Voltage
DAC (VID0 - VID3) Input High Voltage
VID Pull-Up
CHANNEL GENERATOR
Frequency, F
SW
Adjustment Range
Disable Voltage
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
I
SEN
Full Scale Input Current
Over-Current Trip Level
POWER GOOD MONITOR
Under-Voltage Threshold
Under-Voltage Threshold
PGOOD Low Output Voltage
PROTECTION
Over-Voltage Threshold
Percent Over-Voltage Hysteresis
VSEN Rising
VSEN Falling after Over-Voltage
1.12
-
1.15
2
1.2
-
V
DAC
%
VSEN Rising
VSEN Falling
I
PGOOD
= 4mA
-
-
-
0.92
0.90
0.18
-
-
0.4
V
DAC
V
DAC
V
-
-
50
82.5
-
-
µA
µA
R
L
= 10K to Ground
C
L
= 100pF, R
L
= 10K to Ground
C
L
= 100pF, Load =
±400µA
R
L
= 10K to ground, Load = 400µA
R
L
= 10K to ground, Load = -400µA
-
-
-
3.6
-
72
18
5.3
4.1
0.16
-
-
-
-
0.5
dB
MHz
V/µs
V
V
R
T
= 100kΩ,
±1%
See Figure 10
Maximum voltage at FS/DIS to disable controller. I
FS/DIS
= 1mA.
245
0.05
-
275
-
-
305
1.5
1.0
kHz
MHz
V
Percent system deviation from programmed VID Codes
DAC Programming Input Low Threshold Voltage
DAC Programming Input High Threshold Voltage
VIDx = 0V or VIDx = 3V
-1
-
2.0
10
-
-
-
20
1
0.8
-
40
%
V
V
µA
5
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