PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVHSTL F
REQUENCY
S
YNTHESIZER
F
EATURES
• Four LVHSTL outputs (VOHmax = 1.2V)
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS8422004I-01 is a 4 output LVHSTL
IC
S
Synthesizer optimized to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member
o f t h e H i Pe r C l o c k s
T M
f a m i l y o f h i g h
performance clock solutions from ICS. Using
a 25MHz 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS8422004I-01 uses ICS’ 3
rd
generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS8422004I-01 is packaged in a small
24-pin TSSOP package.
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
M Divider
Value
25
25
25
25
N Divider
Value
4
5
10
not used
M/N
Divider Value
6.25
5
2.5
Output
Frequency
(25MHz Ref.)
156.25
125
62.5
not used
P
IN
A
SSIGNMENT
nQ1
Q1
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
V
DD
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
F_SEL1 F_SEL0
0
0
1
1
0
1
0
1
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
Pulldown
25MHz
ICS8422004I-01
2
TEST_CLK
1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1
Not Used
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0
Top View
nQ0
Q1
nQ1
0
Q2
nQ2
M = 25 (fixed)
Q3
nQ3
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8422004AGI-01
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 14, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVHSTL F
REQUENCY
S
YNTHESIZER
Type
Description
Differential output pair. LVHSTL interface levels.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
DDO
Q0, nQ0
MR
Output
Power
Ouput
Input
7
8, 18
9
10, 12
11
13, 14
1 5, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
GND
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
8422004AGI-01
www.icst.com/products/hiperclocks.html
2
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVHSTL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
90
10
0
Maximum
3.465
3.465
2.0
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
80
10
0
Maximum
2.625
2.625
2.0
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 1.8V±0.2V,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465
or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
-150
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
µA
8422004AGI-01
www.icst.com/products/hiperclocks.html
3
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVHSTL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
1.0
0
40
0.6
Typical
Maximum
1.2
0. 4
60
1.1
Units
V
V
%
V
T
ABLE
3D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
3E. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
40
0.9
Test Conditions
Minimum
1.0
0.235
60
Typical
Maximum
1.2
Units
V
V
%
V
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
22.4
Test Conditions
Minimum
Typical
25
Maximum
27.2
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
8422004AGI-01
www.icst.com/products/hiperclocks.html
4
REV. B NOVEMBER 14, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8422004I-01
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVHSTL F
REQUENCY
S
YNTHESIZER
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
140
112
56
TBD
156.25MHz, (1.875MHz - 20MHz)
0.44
0.48
0.49
410
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20% to 80%
Typical
Maximum
170
136
68
Units
MHz
MHz
MH z
ps
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%,V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
sk(o)
t
jit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 3
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter (Random);
NOTE 2
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
62.5MHz,(1.875MHz - 20MHz)
20% to 80%
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
140
112
56
TBD
0.41
0.49
0.50
380
Typical
Maximum
170
136
68
Units
MHz
MHz
MH z
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2 Please refer to the Phase Noise Plot.
NOTE 3 This parameter is defined in accordance with JEDEC Standard 65.
8422004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 14, 2005
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