CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V+ = 36V, Channels 1 and 2, T
J
= 0
o
C to +110
o
C; Unless Otherwise Specified
SYMBOL
DEVICE PARAMETERS
I+
V
DDA
Supply Current
Internal Regulator Output
Voltage
V+ = 42V, PSEN = 12V
V+ = 30V to 42V, I
OUT
= 0mA
V+ = 30V to 42V, I
OUT
= 30mA
SLRN = 12V, I
OUT
= 0mA
VINP
R
VINP
Reference Voltage
VINP Resistance
VDDA = SLRN = 12V, I
VINP
= 0mA
VINP = 0
-
11.7
11.5
11.5
5.01
-
24.7
-
-
-
5.1
900
30
13.3
13.3
13.3
5.19
-
mA
V
V
V
V
Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIERS
| V
IO
|
R
IN
VREG
g
m
(VREG)
g
m
(SFST)
I
VCMP
Input Offset Voltage
(REG - VINP)
Input Resistance to GND
VREG Transconductance
(I
VCMP
/(VREG - VINP)
SFST Transconductance
I
VCMP
/(VREG - SFST)
Maximum Source Current
Maximum Sink Current
OVTH
CLOCK
fq
V
TH
CKIN
Internal Clock Frequency
External Clock Input Threshold
Voltages
XCKS = 12V, V
DDD
= 12V
0.9
33
1.0
-
1.1
66
MHz
%V
DDD
Over-Voltage Threshold
I
VCMP
= 0mA
VREG = 5.1V
VCMP = 1V to 8V, SFST = 11V
V
SFST
< 4.9V
VREG = 4.95V, VCMP = 8V
VREG = 5.25V, VCMP = 0.4V
Voltage at VREG for FLTN to be
latched
-
39
15
0.8
-2.5
0.75
6.05
-
-
30
-
-
-
-
10
85
50
6
-0.75
2.5
6.5
mV
kΩ
mS
mS
mA
mA
V
DMOS TRANSISTORS
r
DS(on)
I
DSS
Drain-Source On-State
Resistance
Drain-Source Leakage Current
I Drain = 2.5A, V
DDD
= 11V,
T
J
= +25
o
C
Drain to Source Voltage = 60V
-
-
-
1
0.22
100
Ω
µA
CURRENT CONTROLED PWM
|V
IO
| VCMP
Buffer Offset Voltage (VCOMP -
V
IFRO
)
IFRO = 0mA to -5mA,
VTCN = 0.2V to 7.6V,
VCMP2 = 0.2V to 7.6V
-
-
125
mV
3
HIP5062
Electrical Specifications
V+ = 36V, Channels 1 and 2, T
J
= 0
o
C to +110
o
C; Unless Otherwise Specified
(Continued)
SYMBOL
V
TH
IFRO
PARAMETER
Voltage at IRFO that disables
PWM. This is due to low load
current
Voltage at IRFO to enable SHRT
output current. This is due to
Regulator Over Current Condi-
tions
SHRT Output Current, During
Over-Current
Threshold voltage on SHRT to
set FLTN latch
I
PEAK
(DMOS
DRAIN
)/I
IRFI
IRFI Resistance to GND
Current Comparator Response
Time (Note 1)
Minimum Controllable Pulse
Width (Note 1)
Minimum Controllable DMOS
Peak Current (Note 1)
V
IRFO
= 7.7V
V
DDD
= 11V
∆I
(DMOS
DRAIN
)/∆t = 1A/ms
I
IRFI
= 2mA
∆I
(DMOS
DRAIN
)/∆t > 1A/µs
TEST CONDITIONS
MIN
116
TYP
-
MAX
250
UNITS
mV
I
TH
IFRO
6.85
-
7.65
V
I
SHRT
V
TH
SHRT
I
GAIN
R
IRFI
t
RS
MCPW
MCPI
START-UP
V+
-75
-
2.0
150
-
25
125
-
5
-
-
30
50
250
-33
-
3.2
360
-
100
500
µA
V
A/mA
Ω
ns
ns
mA
Rising V+ Power-On Reset
Voltage
Falling V+ Power-Off Set
Voltage
V+ Power-On Hysteresis
23
-
9.5
V
DDD
= 11V
3.6
-
V
SFST
= 0V to 11V
SFST = 11V, PSOK = 12V
SFST = 0V, I
PSOK
= 1mA
V
DDD
= 11V
-1.5
-1
-
8.1
-
15
-
-
12
-1.0
-
-
-
26.3
-
11.8
6.5
-
-0.65
1
0.4
9.9
V
V
V
V
KΩ
µA
µA
V
V
V
TH
PSEN
r
PSEN
I
SFST
I
PSOK
V
PSOK
V
TH
SFST
Voltage at PSEN to Enable
Supply
Internal Pull-Up Resistance, to
V
DDD
Soft-Start Charging Current
PSOK High-State Leakage
Current
PSOK Low-State Voltage
PSOK Threshold, Rising V
SFST
THERMAL MONITOR
TEMP
NOTE:
1. Determined by design, not a measured parameter.
Substrate Temperature for
Thermal Monitor to Trip (Note 1)
TMON = 0V
105
-
135
o
C
4
HIP5062
Pin Descriptions
PAD NUMBER
1, 4, 7
2, 3, 5, 6
8
DESIGNATION
S2
D2
V
DDP2
DESCRIPTION
Source pads for the channel 2 regulator.
Drain pads for the channel 2 regulator.
This pad is the power input for the channel 2 DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a 0.1µF chip capacitor placed close to this pad and the DMOS source pads.
Output of the second channel transconductance amplifier. This node is used for both gain and
frequency compensation of the loop.
This pad provides delayed positive indication when both supplies are enabled.
Input to the transconductance error amplifier. The other common input for both amplifiers is
VINP, Pad 36.
This is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when over-
temperature, over-voltage or over-current is experienced. V+ must be powered down to reset.
This terminal is provided to activate the converter. When the input is low, the DMOS drivers are
disabled. There is an internal 12K pull-up resistor on this terminal.
50µA is internally applied to this node when there is an over-current condition.
Control input to internal regulator that is used during the “start-up” of the supply. In normal oper-
ation this terminal starts at 0V and shuts down the internal regulator at approximately 9V. This
pad is usually connected to SFST, pad 16.
Controls the rate of rise of both output voltages. Time is determined by an internal 1µA current
source and an external capacitor.
Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.
This is the analog supply and internal 12V regulator output usually used only during the start-up
sequence. The internal regulator reduced to a nominal 9.2V when SLRN is returned to 12V. Out-
put current capability is 30mA at both voltages.
Input to channel one transconductance error amplifier. The other, common input for both ampli-
fiers is VINP, pad 36.
This pad is the power input for the channel 1 DMOS gate driver and also is used to decouple the
high current pulses to the output driver transistors. The decoupling capacitor should be at least
a 0.1µF chip capacitor placed close to this pad and the DMOS source pads.
Drain pads for the channel 1 regulator.
Source pads for the channel 1 regulator.
Input to transconductance amplifier buffer for channel 1 only. Normally connected to VCMP1,
pad 29.
Output of the first channel transconductance amplifier. This node is used for both gain and fre-
quency compensation of the loop.
A resistor placed between this pad and IRFI1 converts the VCMP1 signal to a current for the cur-
rent sense comparator. The maximum current is set by the value of the resistor, according to the
equation: I
PEAK
= 16/R. Where R is the value of the external resistor in KΩ and must be greater
than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will
be 8.8A. This assumes VCMP1 is 7.3V. Maximum output current should be kept below 10A.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
