CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
SYMBOL
V
DD
= V
G
=12V, V
C
= 5V, V
FB
= 5.1V, SOURCE = GND = DRAIN = 0V, T
J
= 0
o
C to +105
o
C,
Unless Otherwise Specified
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
DEVICE PARAMETERS
I
DD
I
DD
IV
G
IV
G
V
DDC
V
REF
AMPLIFIERS
|I
FB
|
g
m
(V
FB
)
IV
CMAX
IV
CMAX
A
OL
V
CMAX
V
CHYS
IVC
OVER
CLOCK
fq
Internal Clock Frequency
210
250
290
kHz
Input Current
V
FB
Transconductance
I
VC
/(V
FB
- V
REF
)
Maximum Source Current
Maximum Sink Current
Voltage Gain
Short Circuit Recovery Compara-
tor Rising Threshold Voltage
Short Circuit Recovery
Comparator Hysteresis Voltage
V
C
Over-Voltage Current
V
DD
= V
G
= 10.8V, V
C
= V
CMAX
V
FB
= V
REF
/I
VC
/ = 500µA, Note 3
V
FB
= 4.6V
V
FB
= 5.6V
/I
VC
/ = 500µA, Note 3
-
20
-4
1
44
5.4
0.7
0
-0.85
30
-1.8
1.8
50
6.6
1.1
10
0.5
43
-1
4
-
8.9
1.8
25
µA
mS
mA
mA
dB
V
V
mA
Quiescent Supply Current
Operating Supply Current
Quiescent Current to Gate Driver
Operating Current to Gate Driver
Clamp Voltage
Reference Voltage
V
DD
= V
G
= 13.2V, V
C
= 0V,
V
FB
= 4V
V
DD
= V
G
= 13.2V, V
C
= 8.5V, V
FB
= 4V
V
DD
= V
G
= 13.2V, V
C
= 0V
V
C
= 3V
I
DD
= 100mA
I
VC
= 0µA, V
C
= V
FB
6
-
-
-
13.3
5.0
12
24
0
1
14
5.1
18
31
10
2
15
5.2
mA
mA
µA
mA
V
V
DMOS TRANSISTOR
r
DS
(ON)
r
DS
(ON)
I
DSS
I
DSH
C
DRAIN
Drain-Source On-State
Resistance
Drain-Source On-State
Resistance
Drain-Source Leakage Current
Average Drain Short Circuit
Current
DRAIN Capacitance
I
DRAIN
= 5A, V
DD
= V
G
= 10.8V
T
J
= +25
o
C
I
DRAIN
= 5A, V
DD
= V
G
= 10.8V
T
J
= +105
o
C
V
DRAIN
= 60V
V
DRAIN
= 5V, Note 4
Note 4
-
-
-
-
-
0.15
-
0.5
-
200
0.22
0.33
10
5
-
Ω
Ω
µA
A
pF
7-54
Specifications HIP5061
Electrical Specifications
SYMBOL
V
DD
= V
G
=12V, V
C
= 5V, V
FB
= 5.1V, SOURCE = GND = DRAIN = 0V, T
J
= 0
o
C to +105
o
C,
Unless Otherwise Specified
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
CURRENT CONTROLLED PWM
g
m
(V
C
)
V/I
REF
t
BT
t
ONMIN
t
OFFMIN
MinCI
MaxCI
MaxCI
∆I
DRAIN, PEAK
/∆V
C
Voltage to Current Converter Ref-
erence Voltage
Current Comparator Blanking
Time
Minimum DMOS “ON” Time
Minimum DMOS “OFF” Time
Minimum Controllable DMOS
Peak Current
Maximum Controllable DMOS
Peak Current
Maximum Controllable DMOS
Peak Current
Note 3
I
DRAIN
= 0.25A, Note 3
Note 3
Note 3
Note 3
Note 3
Duty Cycle = 6% to 30%, Note 3
Duty Cycle = 30% to 96%, Note 3
1.4
2.4
40
60
40
-
7
5
2.2
2.8
100
150
125
100
9.5
8
3.0
3.1
175
250
200
250
12
12
A/V
V
ns
ns
ns
mA
A
A
CURRENT COMPENSATION RAMP
∆I/∆t
t
RD
START-UP
V
DDMIN
V
DDHYS
V
CEN
R
VC
Rising V
DD
Threshold Voltage
Power-On Hysteresis
Enable Comparator Threshold
Voltage
Power-Up Resistance
4V < V
DD
< 10.8V, V
C
= 0.8V
V
FB
= 4V
V
FB
= 4V
9.3
0.3
1.0
50
10.3
0.45
1.5
500
10.8
0.6
2.0
3000
V
V
V
Ω
Compensation Ramp Rate
Compensation Ramp Delay
∆I
DRAIN, PEAK
/∆Time, Note 3
Note 3
-1.4
1.3
-0.85
1.5
-0.45
1.8
A/µs
µs
THERMAL MONITOR
T
J
T
JHY
NOTES:
1. All Voltages relative to pin 1, GND.
2. V
D
= 10V, Starting T
J
= +25
o
C, L = 4mH, I
PEAK
= 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
Substrate Temperature for
Thermal Monitor to Trip
Temperature Hysteresis
Note 4
Note 4
105
-
-
5
145
-
o
C
o
C
TABLE 1.
CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
I
L
(PEAK AMPS)
5
7
10
12.5
7
L
+
V
D
V
D
(V)
10
10
6
6
NOTE:
L (mH)
40
4TZ
0.33
0.14
EAS (mJ)
550
120
18
12
HIP5061
I
L
-
1
VARY t
P
TO OBTAIN
REQUIRED PEAK I
L
12V
t
P
Device Selected to Obtain Peak Current without Clocking
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
7-55
HIP5061
Definitions of Electrical Specifications
Refer to the Functional Block Diagram of Figure 1 for loca-
tions of functional blocks and devices.
Device Parameters
I
DD
, Quiescent Supply Current
- Supply current with the
chip disabled. The Clock, Error Amplifier, Voltage-to-Current
Converter, and Current Ramp circuits draw only quiescent
current. The supply voltage must be kept lower than the
turn-on voltage of the V
DD
clamp or else the supply current
increases dramatically.
I
DD
, Operating Supply Current
- Supply current with the
chip enabled. The Error Amplifier is drawing its maximum
current because V
FB
is less than its reference voltage. The
voltage-to-current amplifier is drawing its maximum because
V
C
is at its maximum. The ramp circuit is drawing its maxi-
mum because it is not being disabled by the DMOS transis-
tor turning off.
IV
G
, Quiescent Gate Driver Current
- Gate Drivers supply
current with the IC disabled. The Gate Driver is not toggling
and so it draws only leakage current.
IV
G
, Operating Gate Driver Current
- Gate Drivers supply
current with the IC enabled. The DMOS transistor drain is
loaded with a large resistor tied to 60V so that it is swinging
from 0V to 60V during each cycle.
V
DDC
, V
DD
Clamp
- V
DD
voltage at the maximum allowed
current through the V
DD
Clamp.
V
REF
, Reference Voltage
- The voltage on FB that sets the
current on V
C
to zero. This is the reference voltage for the
DC/DC converter.
Amplifiers
|I
FB
|, Input Current
- Current through FB pin when it is at its
normal operating voltage. This current must be considered
when connecting the output of a DC/DC convertor to the FB
pin via a resistor divider.
g
m
(V
FB
), Transconductance
- The change in current
through the V
C
pin divided by the change in voltage on FB.
The g
m
times the resistance between V
C
and ground gives
the voltage gain of the Error Amplifier.
IV
CMAX
, Maximum Source Current
- The current on V
C
when FB is more than a few hundred millivolts less than
V
REF
.
IV
CMAX
, Maximum Sink Current
- The current on V
C
when
FB is more than a few hundred millivolts more than V
REF
.
A
OL
, Voltage Gain
- Change in the voltage on V
C
divided by
the change in voltage on FB. There is no resistive load on
V
C
. This is the voltage gain of the error amplifier when g
m
times load resistance is larger than this gain.
V
CMAX
, V
C
Rising Threshold
- The voltage on V
C
that
causes the Voltage-to-Current Amplifier to reach full-scale.
When V
C
reaches this voltage, the V
C
NMOS transistor (tran-
sistor with its drain connected to the V
C
pin in the Functional
Block Diagram of Figure 2) turns on and tries to lower the volt-
age on V
C
.
V
CHYS
, V
CMAX
Hysteresis
- The voltage on V
C
that causes
the NMOS transistor to turnoff if it had been turned on by V
C
exceeding V
CMAX
. At this voltage the current out of the Voltage-
to-Current Converter is at roughly three quarters of full-scale.
IVC
OVER
, V
C
Over-Voltage Current
- The current drawn
through the V
C
pin after the NMOS transistor is turned on
due to excessive voltage on V
C
. The NMOS transistor con-
nected to the V
C
pin draws more than enough current to
overcome the full scale source current of the Error Amplifier.
Clock
fq, Frequency
- The frequency of the DC/DC converter. The
Clock actually runs faster than this value so that various con-
trol signals can be internally generated.
DMOS Transistor
r
DS(ON)
, “On” Resistance
- Resistance from DMOS transis-
tor Drain to Source at maximum drain current and minimum
Gate Driver voltage, V
G
.
I
DSS
, Leakage Current
- Current through DMOS transistor
at the Maximum Rated Voltage.
Current Controlled PWM
g
m
(V
C
), Transconductance
- The change in the DMOS tran-
sistor peak drain current divided by the change in voltage on
V
C
. When analyzing DC/DC converters the DMOS transistor
and the inductor tied to the drain are sometimes modelled as
a voltage-controlled current source and this parameter is the
gain of the voltage-controlled current source.
V/I
REF
, Current Control Threshold
- The voltage on V
C
that causes the DMOS transistor to shut off at the minimum
controllable current. This voltage is greater than the Enable
Comparator Threshold (V
CEN
) so that as V
C
rises the IC
does not jump from the disabled state to the DMOS transis-
tor conducting a large current.
t
BT
, Blanking Time
- At the beginning of each cycle there is
a blanking time that the DMOS transistor turns-on and stays-
on no matter how high drain the current. This blanking time
permits ringing in the external parasitic capacitances and
inductances to dampen and for the charging of the reverse
bias on the rectifier diode.
t
ONMIN
, Minimum DMOS Transistor “On” Time
- The mini-
mum on-time for the DMOS transistor where small changes
in the V
C
voltage make predictable changes in the DMOS
transistor peak current. Converters should be designed to
avoid requiring pulse widths less than the minimum on time.
t
OFFMIN
, Minimum DMOS Transistor “Off” Time
- The min-
imum off-time for the DMOS transistor that allows enough time
for the IC to get ready for the next cycle. Converters should be
designed to avoid requiring pulse widths so large that the mini-
mum off time is violated. (However, zero off time is allowed, that
is, the DMOS transistor can stay on from one cycle to the next.)
MinCI, Minimum Controllable Current
- When the voltage
on V
C
is below V/I
REF
, the peak current for the DMOS tran-
sistor is too small for the Current Comparator to operate reli-
ably. Converters should be designed to avoid operating the
DMOS transistor at this low current.
7-56
HIP5061
MaxCI, Maximum Controllable Current
- The peak current
for the DMOS transistor when the Voltage-to-Current Con-
verter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the Current Ramp becoming active.
Current Compensation Ramp
∆I/∆t,
Compensation Ramp Rate
- At a given voltage on V
C
the DMOS transistor will turn off at some current that stays
constant for about the first 1.5µs of the cycle. After 1.5µs, the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
t
RD
, Compensation Ramp Delay
- The time into each cycle
that the compensation ramp turns on. The Current Compen-
sation Ramp, used for Slope Compensation, is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
Start-Up
V
DDMIN
, Rising V
DD
Threshold Voltage
- The minimum
voltage on V
DD
needed to enable the IC.
V
DDHYS
, Power - On Hysteresis Voltage
- The difference
between the voltage on V
DD
that enables the IC and the volt-
age that disables the IC.
V
CEN
, Enable Comparator Threshold Voltage
- The mini-
mum voltage on V
C
needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the V
C
pin to GND.
R
VC
, Power - Up Resistance
- When V
DD
is below V
DDMIN
,
the NMOS transistor connected to the V
C
pin is turned on to
make sure the V
C
node is low. Thus the voltage on V
C
can
gradually build up as will the trip current on the DMOS tran-
sistor. This is the only form of “soft start” included on the IC.
The resistance is measured between the V
C
and GND pins.
Thermal Monitor
T
J
, Rising Temperature Threshold
- The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions, especially during start-up when the DMOS tran-
sistor may stay on for a long time if an external soft-start cir-
cuit is not added.
T
JHY
, Temperature Hysteresis
- The IC must cool down
this much after it is disabled by being too hot before it can
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