1. PV+ and SV+ are to be tied together, as are PGND and SGND.
2. Operating above the continuous current rating causes a decrease in operating life.
3. Derate power dissipation above case temperature of +75
o
C at 0.33 Watts/
o
C.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS
SUPPLY (SV+) CURRENT
No Drive
With Drive
LOGIC INPUT CURRENT
Sensor Inputs
Brake Input
LOGIC INPUT THRESHOLDS
Sensor Inputs
Sensor Inputs
Brake Input
Brake Input
AMPLIFIER INPUT (SPD)
Bias Current
Offset Voltage
Input Range (Linear)
Input Impedance
System Bandwidth
Current Limit
THERMAL LIMIT
Threshold
Hysteresis
OUTPUT DRIVERS
On Saturation (See Note 5)
On Saturation (See Note 5)
Off Leakage
Slew Rate
T
A
= +25
o
C and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified
TEST CONDITION
MIN
TYP
MAX
UNITS
Outputs Off
Outputs On
-
-
-
-
10
15
mA
mA
SENA, SENB & SENC = 0V to 3V
FBRK = 0.8V to 2.4V
-0.5
50
-
-
-1.5
150
mA
µA
Logic “0” Input Voltage
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Voltage
-
3
-
2.4
-
-
-
-
1.8
-
0.8
-
V
V
V
V
-
-
0
1
(Note 1)
Rsense = 0.20Ω
-
-
-
-
-
-
35
5
700
3
1
-
-
-
nA
mV
V
MΩ
kHz
A
-
-
155
40
-
-
o
C
o
C
I
OUT
= 3A, V
PMOS
+ V
NMOS
I
OUT
= 0.6A, V
PMOS
+ V
NMOS
PV+ > V
OUT
> PGND or I
SEN
(See Note 2)
-
-
-
-
-
-
-
0.5
2.2
0.44
1
-
V
V
mA
V/µS
6-12
HIP4011
Electrical Specifications
PARAMETERS
FREEWHEEL DIODES
Forward Drop
INTERNAL BRAKE DRIVER
Undervoltage Trip Point, PV+
Hysteresis
On Saturation
BRAKE CAPACITOR (BCAP)
Discharge Leakage
SV+ = PV+ = 3V to 12V, BCAP = 10V
-
-
5
µA
(See Note 3)
(See Note 4)
Each N
MOS
, I
OUT
= 3A
2.7
40
-
-
-
-
3.3
60
0.4
V
%
V
I
OUT
= 1A
-
-
1.5
V
T
A
= +25
o
C and SV+ = PV+ = 10.4V to 13.2V, Unless Otherwise Specified
(Continued)
TEST CONDITION
MIN
TYP
MAX
UNITS
NOTES:
1. The system bandwidth is fixed by an internal RC network around the amplifier.
2. Internal limiting of turn on and turn off drive is used to limit output dv/dt.
3. The braking action starts at the given trip point with a falling supply voltage.
4. Hysteresis causes the brake to be removed at a higher trip point with a rising supply voltage.
5. This value includes the combined voltage drops of one upper plus one lower switch at the indicated current.
Functional Block Diagram
SIGNAL
V+
BCAP
13
1mA
SENA
1
HALL
SENSOR
A
1mA
SENB
2
HALL
SENSOR
B
V+
VBS (BRAKE
(SENSE REF)
V+
10
4 PV+
9 PV+
OUTA
11
V+
DECODE
LOGIC
WITH
ILLEGAL
CODE
REJECTION
OUTB
8
MOTOR
φB
BRAKE
CAP.
POWER V+
MOTOR
φA
V+
1mA
CURRENT
LIMITING
V
CL
(CURRENT LIMITING
REF)
+
38.5K
-
C
1
100pF
R
1
R
2
39K
39K
1K 1K
OUTC
5
ISEN
12
ISEN
7
CURRENT
SENSE
RESISTOR
MOTOR
φC
SENC
3
HALL
SENSOR
C
FORCE
BRAKE
FBRK
6
BREAK
BEFORE
MAKE
100µA
IREF
14
THERMAL
SENSING
PGND
TAB
SUBSTRATE
GND
15
SIGNAL
SGND
GND
6-13
HIP4011
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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