CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETERS
POWER SUPPLY
Logic Supply Quiescent Current
V
CC
Threshold for POR Reset
V
CC
= 4.5V to 5.5V, V
PWR
= 5.5V to 17V, T
A
= -40
o
C to +125
o
C, Unless Otherwise Specified
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
V
POR
PI0-5 High (ON), Increase V
CC
, Measure
V
CC
Threshold When Gate Drive Goes
High
PI0-5 High, Decrease V
CC
, Measure V
CC
Threshold when Gate Drive goes Low,
Hysteresis Equals Differential V
CC
Voltage
for Gate Drive High to Gate Drive Low
V
PWR
= 14V
V
PWR
= 14V
V
PWR
Threshold Measured When Gate
Drive Voltage, V
G
Goes Low
-
3.5
-
4
5
4.25
mA
V
POR Hysteresis
V
POR_HYS
-
500
-
mV
Undervoltage Lockout, Low V
CC
Battery Supply Monitor Current
V
PWR
Over-Voltage Shutdown
Threshold
V
PWR
Over-Voltage Shutdown
Hysteresis
LOGIC INPUTS
Input High Voltage; SI, SCK, CS
Input Low Voltage; SI, SCK, CS
Input Leakage Current; SI, SCK
Input Pulldown Currents;
PI0-5, HPW01, HPW45
Input Pullup Currents; CS, HLOS
Threshold Voltage at Falling Edge,
PI0-5, HLOS, HPW01, HPW45
Threshold Voltge at Rising Edge,
PI0-5, HLOS, HPW01, HPW45
Input Hysteresis Voltage;
PI0-5, HLOS, HPW01, HPW45
Input Capacitance, SCK, SI
DATA OUTPUT
SO Data Output High Voltage
SO Data Output Low Voltage
SO Three-State Leakage Current
SO Three-State Capacitance
V
CC
I
PWR
V
PWR_OVTH
V
PWR_OVHYS
1
-
30
-
2
-
35
1
3.7
150
40
-
V
µA
V
V
V
IH
V
IL
I
LK
I
IN_PD
I
IN_PU
V
T
-
V
T
+
V
IN_HYS
C
IN
0 < V
IN
< V
CC
0.3V
CC
< V
IN
< V
CC
GND < V
IN
< 0.7 V
CC
0.7V
CC
-
-10
3
-25
1.5
1.8
250
-
-
-
0
10
-10
2.2
2.6
500
7
-
0.3V
CC
10
25
-2
3.0
3.4
650
12
V
V
µA
µA
µA
V
V
mV
pF
V
OH
V
OL
I
SOT
C
SOT
I
O
= 5mA Source Current
I
O
= 5mA Sink Current
V
CC
= 0V to 5.5V
0 < V
IN
< V
CC
0.8V
CC
-
-10
-
-
0.2
1
15
-
0.4
10
20
V
V
µA
pF
3
Specifications HIP0063
Electrical Specifications
PARAMETERS
GATE DRIVE OUTPUT
Gate Drive Output Source Current
Gate Drive Output Sink Current
Gate Drive Rise Time with Load
Output Turn-ON Delay, Rising Edge
of CS to 10% of V
G
Turn-ON
Output Turn-OFF Delay, Rising Edge
of CS to 10% of V
G
Turn-OFF
I
GOH
I
GOL
t
R
t
PHL
t
PLH
V
G
= 0V
V
G
= 4.5V
Cap. Load, Gate to GND = (TBD)pF
-4.4
0.2
TBD
-
-
-
-
TBD
5
5
-0.5
3.3
-
10
10
mA
mA
µs
µs
µs
V
CC
= 4.5V to 5.5V, V
PWR
= 5.5V to 17V, T
A
= -40
o
C to +125
o
C, Unless Otherwise Specified
(Continued)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRAIN MONITOR INPUT AND PROTECTION
D0-5 Drain Monitor Clamp Voltage
V
DM
D0-5 Clamp Current, I
DM
= 2mA;
t
PW
=100µs, Duty Cycle <1%, Gate Drive
Voltage, V
G
Low (Note 2)
0.3V
CC
< V
DM
< V
CC
58
64
74
V
D0-5 Drain Monitor Pulldown Current
Sink
Fault Threshold Voltage Sensed at
the Drain Monitor Input, Shorts/Opens
Short Circuit Sense Fault Time
V
DM
> V
DM_FTH
, Gate ON/High
Over-Current Refresh Time During
Short Circuit (Gate Drive OFF)
Over-Current ON Time Duty Cycle
Open-Load “OFF” Sense Time
V
DM
< V
DM_FTH
, Gate OFF/Low
I
DM
V
DM_FTH
t
SC_ON
3
0.3V
CC
10
0.4V
CC
28
28
16.4
16.4
0.34
28
25
0.5V
CC
39
36
21.4
19.6
0.37
39
µA
V
µs
µs
ms
ms
%
µs
T
A
= -40
o
C to 25
o
C
T
A
= 25
o
C to 150
o
C
18
19
11.4
12.0
0.31
18
t
SC_REF
T
A
= -40
o
C to 25
o
C
T
A
= 25
o
C to 150
o
C
Duty Cycle = t
SC
/(t
SC
+ t
REF
)
t
OL_OFF
NOTE:
1. Refer the Figure 3 recommended application circuit for V
PWR
protection given system power supply conditions of +24V for double bat-
tery voltage, -14V for reverse battery voltage and +80V system level load dump voltages.
2. V
DM
refers to the specified Drain Monitor voltage input at pins D0 thru D5, that monitor the drain status from the respective external
MOSFET.
3. V
G
refers to the specified Gate Drive voltage at the output pins, G0 thru G5, that drive the Gate of the respective external MOSFET.
+5V
0.01µF
V
CC
PI0
PI1
PI2
PI3
PI4
PI5
CS
SI
SCK
SO
HLOS
HPW01
HPW45
V
PWR
D0
G0
D1
G1
G2
D2
D3
G3
G4
D4
G5
D5
GND
0.01µF
27V
0.01µF
LOAD:
13Ω, 6.8µH
ONE OF SIX
OUTPUTS
V
BATT
HIGH SPEED
PARALLEL
DATA INPUT
CHIP SELECT
SPI BUS
SERIAL
INPUT
PWM SELECT
HARDWARE
GENERATED
PWM INPUT
FIGURE 3. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING THE V
PWR
SUPPLY INTERFACE WITH CIRCUIT PRO-
TECTION COMPONENTS. FOR THE VALUES SHOWN, GIVEN A LOAD DUMP OF 80V THAT DECAYS TO THE V
PWR
LEVEL IN 350ms, THE 27V ZENER DIODE IS REQUIRED TO CLAMP THE TRANSIENT TO 60V MAXIMUM. FOR THE
REVERSE BATTERY PROTECTION, THE ZENER DIODE CLAMPS NEGATIVE VOLTAGES
4
Specifications HIP0063
Serial Peripheral Interface Timing
PARAMETERS
Clock Operating Frequency
Clock Period
Clock High Time
Clock Low Time
Falling Edge of CS to Rising Edge of SCK
Falling Edge of SCK to Rising Edge of CS
SI to SCK Setup Time
(See Figure 4)
SYMBOL
f
SCK
t
SCK
t
WH
t
WL
t
LEAD
t
LAG
t
SU2
C
L
= 200pF
SCK = 0.8V to 0.8V
SCK = 2V TO 2V; f
SCK
= 1.8MHz
SCK = 0.8V TO 0.8V; f
SCK
= 1.8MHz
CS = 0.8V to SCK = 2V
SCK = 0.8V to CS = 2V
SI = 0.8, 2V to SCK = 2V;
f
SCK
= 2.25MHz
SCK = 2V to SI Hold
C
L
= 200pF
C
L
= 200pF
SO = 0.8, 2V to SCK = 0.8V; C
L
= 200pF
SO = 0.8, 2V to SCK = 0.8V; C
L
= 200pF
C
L
= 200pF
C
L
= 200pF
CS = 0.8V to SO Low Impedance
TEST CONDITION
MIN
1.8
-
-
-
-
-
-
TYP
4
250
100
100
150
50
25
MAX
-
555
248
248
200
200
55
UNITS
MHz
ns
ns
ns
ns
ns
ns
SI Hold After SCK Rise
Rise Time of Incoming Signals
Fall Time of Incoming Signals
SO Data Valid to Falling Edge of SCK
Falling Edge of SCK to SO
Rise Time of SO
Fall Time of SO
Falling Edge of CS to SO Operational
(1kΩ Pulldown on SO Pin)
Rising Edge of CS to SO Three-State
(1kΩ Pulldown on SO Pin)
Rising Edge of SCK to SO (Data Valid)
t
H2
t
rSI
t
fSI
t
SU1
t
H1
t
rSO
t
fSO
t
SOEN
-
-
-
80
80
-
-
-
10
-
-
-
125
30
30
150
55
120
120
-
-
50
50
300
ns
ns
ns
ns
ns
ns
ns
ns
t
SODIS
CS = 2V to SO Three-State
-
150
200
ns
t
VALID
C
L
= 200pF, 1.8MHz
-
C
L
= 200pF, 2.25MHz
-
-
-
172
117
ns
ns
CS
t
SCK
t
LEAD
1
2
t
WL
t
VALID
t
SU2
(MSB = 0)
t
H2
LSB
t
WH
X
t
LAG
SCK
SI
t
SODIS
LAST BIT
XMITTED
t
SOEN
SO
MSB
t
SU1
t
H1
LSB
FIGURE 4. TIMING DIAGRAM FOR THE HIP0063 SHOWING THE SPI BUS INPUT CONTROL SIGNALS
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
stm32/stm8
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