CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp voltage V
OC
.
2. The maximum continuous current with all outputs on is limited by package dissipation. At 25
o
C ambient temperature, the maximum equal
current with all outputs ON is 211mA in each output for a total of 1.69A. At a maximum ambient temperature of T
A
= 85
o
C and
r
DSON
(Max) = 3.5Ω, each output is limited to 152mA and the total current for all 8 outputs ON is 8 x 152mA = 1.22A.
3.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
V
CC
= 4.5V to 5.5V, V
BATT
= 8V to 16V, T
A
= -40
o
C to 85
o
C, Unless Otherwise Specified.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Output Clamping Voltage
Output Clamping Energy
Peak Output Load Currents,
Short Duration
Cold Start-up Lamp Currents
Output OFF Leakage Current
Output Rise Time
Output Fall Time
Output Delay from Strobe, High to
Low Output Transition
Output Delay from Strobe, Low to
High Output Transition
LOGIC SUPPLY
Logic Supply Current, Loaded
Logic Supply Current, No Load
I
CC
I
CC
All Outputs ON, 200mA Load at each
Output
All Outputs OFF
-
-
-
-
100
100
µA
µA
r
DS(ON)
V
OC
E
OC
I
PEAK
I
LAMP
I
OFF
t
rise
t
fall
t
DHL
t
DLH
Output Current = 200mA, T
A
= 85
o
C
Outputs OFF
5ms Pulse, T
A
= 25
o
C
100µs Duration, Each Output, all
Outputs ON, Duty Cycle
≤
2%
5ms Duration, Each Output, all
Outputs ON, Duty Cycle
≤
17%
Output Voltage = 40V, T
A
= 85
o
C
Load = 75Ω, 0.01µF (RC in Parallel),
V
BATT
= 18V
42
75
0.85
0.3
-
0.5
0.5
1
0.2
2
50
190
-
-
-0.2
4
10
4
2.6
-
-
10
30
30
10
10
3.5
58
Ω
V
mJ
A
A
µA
µs
µs
µs
µs
2
Specifications HIP0051
Electrical Specifications
PARAMETER
LOGIC INPUTS (EN, SI, SCK, STR)
Threshold Voltage at Falling Edge
Threshold Voltage at Rising Edge
Hysteresis Voltage
Leakage Current
Leakage Current
SERIAL DATA CLOCK (SCK)
Frequency
Pulse Width High
Pulse Width Low
SERIAL DATA IN (SI)
Input Setup Time
Input Hold Time
STROBE (STR)
Strobe Pulse Width
Min. Clock to Strobe Delay
SERIAL DATA OUT (SO)
Low Level Output Voltage
High Level Output Voltage
Propagation Delay
V
OL
V
OH
t
P(CD)
Sink Current = 1.6mA
Source Current = -1.6mA
-
3.7
75
0.2
4.4
260
0.4
-
-
V
V
ns
t
W(S)
t
D(CS)
150
75
12
5
-
-
ns
ns
t
SUI
T
HI
-
-
1.1
1.5
75
75
ns
ns
f
SCK
t
W(CKH)
t
W(CKL)
-
175
175
-
27
27
1.6
-
-
MHz
ns
ns
V
T-
V
T+
V
H
I
LIN
I
LIN
V
CC
= 5V
±
10%
V
CC
= 5V
±
10%
V
T+
- V
T-
V
CC
= 5V
V
CC
= 0V
0.2V
CC
-
0.85
-10
-10
0.3V
CC
0.6V
CC
1.4
-0.2
-0.1
-
0.7V
CC
2.25
10
10
V
V
V
µA
µA
V
CC
= 4.5V to 5.5V, V
BATT
= 8V to 16V, T
A
= -40
o
C to 85
o
C, Unless Otherwise Specified.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
t
W(SCK)
SCK (CLOCK)
t
SUI
SI (SERIAL DATA IN)
t
W(SCK)
t
HI
t
D(CS)
STR (STROBE)
t
DHL
t
DLH
DRx
(POWER OUTPUT DRIVER)
t
P(CD)
SO (SERIAL DATA OUT)
t
W(S)
90%
10%
t
fall
, t
rise
FIGURE 1. LOGIC TIMING CONTROL SPECIFICATIONS
3
HIP0051
Pin Descriptions
V
CC
- Logic Power Supply
The V
CC
pin is the positive 5V logic voltage supply input for
the IC. The normal operating voltage range is 4.5 to 5.5V.
When switched on, the POR forces all outputs off.
SCK - Serial Clock
SCK is the clock input for the SPI interface. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schmitt
trigger.
SI - Serial Data In
SI is the Serial Data Input pin for the SPI interface. The eight
Power Outputs are controlled by the serial data via the
Output Data Buffer. This input has a Schmitt trigger.
STR - Strobe for the SPI Interface
When the STR pin is high, data from the 8-bit shift register is
passed into the Output Data Buffers where it controls the
ON-OFF state of each output driver. The data is latched in
the Output Data Buffers on the trailing edge of the STR
pulse. This input has a Schmitt trigger.
EN - Enable
The Enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the Output Data
Buffer is held low and all output drivers are disabled. When
EN is low, the output drivers are enabled and data in the
8-bit shift register is transparent to the Output Data Buffer.
This input has a Schmitt trigger.
LGND and GND - Ground
LGND is the logic input power supply ground pin. The GND
pins are common grounds for the Power Output Drivers. The
power supplies for the logic and power circuits require a
common ground. To minimize ground bounce at the logic
input, the external ground return path for the GND pin should
be separate from the LGND pin. LGND and GND have com-
mon substrate ground connections on the chip.
SO - Serial Data Out
The Serial Data Out allows other ICs to be serially
cascaded. For example, a 10-bit LED driver may be located
behind the HIP0051. A controlling microprocessor may then
clock out 18 bits of information and simultaneously strobe
both parts. The cascaded ICs may be the same or different
from the HIP0051.
DR0 to DR7 - Outputs 0 Thru 7
The Drain Output pins of the DMOS Power Drivers are
capable of sinking 250mA.
OUTPUT CONTROL TABLE
STROBE
D1
0
1
1
1
1
0
1
D2
0
0
1
1
1
0
1
8-BIT SERIAL DATA (LATCHED)
D3
0
0
0
1
1
0
1
D4
0
0
0
0
1
0
1
D5
0
0
0
0
0
1
1
D6
0
0
0
0
0
1
1
D7
0
0
0
0
0
1
1
D8
0
0
0
0
0
1
1
DR1
OFF
ON
ON
ON
ON
OFF
ON
DR2
OFF
OFF
ON
ON
ON
OFF
ON
DR3
OFF
OFF
OFF
ON
ON
OFF
ON
OUTPUT
DR4
OFF
OFF
OFF
OFF
ON
OFF
ON
DR5
OFF
OFF
OFF
OFF
OFF
ON
ON
DR6
OFF
OFF
OFF
OFF
OFF
ON
ON
DR7
OFF
OFF
OFF
OFF
OFF
ON
ON
DR8
OFF
OFF
OFF
OFF
OFF
ON
ON
4
HIP0051
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
1
2
3
SEATING PLANE
-A-
D
-C-
A
h x 45
o
H
0.25(0.010) M
B M
M20.3
(JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
SYMBOL
A
A1
L
MILLIMETERS
MIN
2.35
0.10
0.33
0.23
12.60
7.40
MAX
2.65
0.30
0.51
0.32
13.00
7.60
NOTES
-
-
9
-
3
4
-
-
5
6
7
8
o
-
Rev. 0 12/93
MIN
0.0926
0.0040
0.013
0.0091
0.4961
0.2914
MAX
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
B
C
D
E
α
A1
0.10(0.004)
C
e
H
h
L
N
0.050 BSC
0.394
0.010
0.016
20
0
o
8
o
0.419
0.029
0.050
1.27 BSC
10.00
0.25
0.40
20
0
o
10.65
0.75
1.27
e
B
0.25(0.010) M
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
α
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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