L67132/L67142
2 K
×
8 CMOS Dual Port RAM 3.3 Volt
Introduction
The L67132/67142 are very low power CMOS dual port
static RAMs organized as 2048
×
8. They are designed to
be used as a stand-alone 8 bit dual port RAM or as a
combination MASTER/SLAVE dual port for 16 bits or
more width systems. The MHS MASTER/SLAVE dual
port approach in memory system applications results in
full speed, error free operation without the need for
additional discrete logic.
Master and slave devices provide two independent ports
with separate control, address and I/O pins that permit
independent, asynchronous access for reads and writes to
any location in the memory. An automatic power down
feature controlled by CS permits the onchip circuitry of
each port in order to enter a very low stand by power
mode.
Using an array of eight transistors (8T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the L67132/67142 combine an
extremely low standby supply current (typ = 1.0
µA)
with
a fast access time at 45 ns over the full temperature range.
All versions offer battery backup data retention capability
with a typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the L67132/67142
is processed according to the methods of the latest
revision of the MIL STD 883 (class B or S) and/or ESA
SCC 9000.
Features
D
Single 3.3 V
±
0.3 volt power supply
D
Fast access time
45(*) ns to 70 ns
D
67132L/67142L low power
67132V/67142V very low power
D
Expandable data bus to 16 bits or more using master/slave
devices when using more than one device
(*) Preliminary
D
D
D
D
D
On chip arbitration logic
BUSY output flag on master
BUSY input flag on slave
Fully asynchronous operation from either port
Battery backup operation :
2 V data retention
MATRA MHS
Rev. D (19 Fev. 97)
1
L67132/L67142
Interface
Pin Configuration
48 PIN DIL (top view), plastic,
ceramic 600 mils
52 PIN PLCC (top view)
48 PIN LCC (top view)
64 PIN VQFP
(top view)
Block Diagram
A
10L
A
10R
Note :
1. L 67132 (MASTER) : BUSY is open drain output and requires pullup resistor
L 67142 (SLAVE) : BUSY in input
2
MATRA MHS
Rev. D (19 Fev. 97)
L67132/L67142
Pin Names
LEFT PORT
CS
L
R/W
L
OE
L
A
0L – 10L
I/O
0L – 7L
BUSY
L
VCC
GND
RIGHT PORT
CS
R
R/W
R
OE
R
A
0R – 10R
I/O
0R – 7R
BUSY
R
NAMES
Chip select
Write Enable
Output Enable
Address
Data Input/Output
Busy Flag
Power
Ground
Functional Description
The L67132/67142 has two ports with separate control,
address and I/0 pins that permit independent read/write
access to any memory location. These devices have an
automatic power-down feature controlled by CS. CS
controls on-chip power-down circuitry which causes the
port concerned to go into stand-by mode when not
selected (CS high). When a port is selected access to the
full memory array is permitted. Each port has its own
Output Enable control (OE). In read mode, the port’s OE
turns the Output drivers on when set LOW.
Non-conflicting READ/WRITE conditions are illustrated in
table 1.
access (refer to table 2). The inhibited port’s BUSY flag
is set and will reset when the port granted access
completes its operation in both arbitration modes.
Data Bus Width Expansion
Master/Slave Description
Expanding the data bus width to 16 or more bits in a
dual-port RAM system means that several chips may be
active simultaneously. If every chip has a hardware
arbitrator, and the addresses for each chip arrive at the
same time one chip may activate its L BUSY signal while
another activates its R BUSY signal. Both sides are now
busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out” problem, MHS has
developed a MASTER/SLAVE system which uses a
single hardware arbitrator located on the MASTER. The
SLAVE has BUSY inputs which allow direct interface to
the MASTER with no external components, giving a
speed advantage over other systems.
When dual-port RAMs are expanded in width, the
SLAVE RAMs must be prevented from writing until the
BUSY input has been settled. Otherwise, the SLAVE chip
may begin a write cycle during a conflict situation. On the
opposite, the write pulse must extend a hold time beyond
BUSY to ensure that a write cycle occurs once the conflict
is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the
same time.
The write pulse to the SLAVE must be inhibited by the
MASTER’s maximum arbitration time. If a conflict then
occurs, the write to the SLAVE will be inhibited because
of the MASTER’s BUSY signal.
Arbitration Logic
The arbitration logic will resolve an address match or a
chip select match down to a minimum of 5 ns and
determine which port has access. In all cases, an active
BUSY flag will be set for the inhibited port.
The BUSY flags are required when both ports attempt to
access the same location simultaneously.Should this
conflict arise, on-chip arbitration logic will determine
which port has access and set the BUSY flag for the
inhibited port. BUSY is set at speeds that allow the
processor to hold the operation with its associated address
and data. It should be noted that the operation is invalid
for the port for which BUSY is set LOW. The inhibited
port will be given access when BUSY goes inactive.
A conflict will occur when both left and right ports are
active and the two addresses coincide. The on-chip
arbitration determines access in these circumstances.
Two modes of arbitration are provided : (1) if the
addresses match and are valid before CS on-chip control
logic arbitrates between CS
L
and CS
R
for access ; or (2)
if the CS are low before an address match, on-chip control
logic arbitrates between the left and right addresses for
MATRA MHS
Rev. D (19 Fev. 97)
3
L67132/L67142
Truth Table
Table 1 : Non Contention Read/Write Control
(4)
LEFT OR RIGHT PORT
(1)
FUNCTION
R/W
X
L
H
H
Notes :
CS
H
L
L
L
OE
X
X
L
H
D0–7
Z
DATA
IN
DATA
OUT
Z
Port Disabled and in Power Down Mode. ICCSB or ICCSB1
Data on Port Written into memory
(2)
Data in Memory Output on Port
(3)
High Impedance Outputs
1. A
OL
– A
10L
≠
A
0R
– A
10R
.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD
and t
DDD
timing.
4. H = HIGH, L = LOW, X = DON’T CARE, Z = HIGH IMPEDANCE.
Table 2 : Arbitration
(5)
LEFT PORT
CS
L
H
L
H
L
RIGHT PORT
CS
R
H
H
L
L
FLAGS
FUNCTION
BUSY
L
H
H
H
H
A
0L
– A
10L
X
Any
X
≠
A
0R
– A
10R
A
0L
– A
10R
X
X
Any
≠
A
0L
– A
10L
BUSY
R
H
H
H
H
No Contention
No Contention
No Contention
No Contention
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L
L
L
L
LV5R
RV5L
Same
Same
L
L
L
L
LV5R
RV5L
Same
Same
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
RL5L
LW5R
LW5R
Notes :
= A
0R
– A
10R
= A
0R
– A
10R
= A
0R –
A
10R
= A
0R
– A
10R
LL5R
RL5L
LW5R
LW5R
= A
0L
– A
10L
= A
0L –
A
10L
= A
0L
– A
10L
= A
0L
– A
10L
H
L
H
L
L
H
L
H
L–Port Wins
R–Port Wins
Arbitration Resolved
Arbitration Resolved
5. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid
≥
5 ns before right address.
RV5L = Right address Valid
≥
5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW
≥
5 ns before Right CS.
RL5L = Right CS = LOW
≥
5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
4
MATRA MHS
Rev. D (19 Fev. 97)
L67132/L67142
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC–GND) : . . . . . . . . . . . . . . . . . . –0.3 V to 7.0 V
Input or output voltage applied : . . . (GND –0.3 V) to (VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
*
Notice
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extented periods may affect reliability.
OPERATING RANGE
Military
Automotive
Commercial
Industrial
OPERATING SUPPLY VOLTAGE
V
CC
= 3.3 V
±
0.3 V
V
CC
= 3.3 V
±
0.3 V
V
CC
= 3.3 V
±
0.3 V
V
CC
= 3.3 V
±
0.3 V
OPERATING TEMPERATURE
– 55
o
C to + 125
o
C
– 40
o
C to + 125
o
C
0
o
C to + 70
o
C
– 40
o
C to + 85
o
C
DC Parameters
L67132/67142–4 L67132/67142–5 L67132/67142–7
5
5
0
Parameter
Description
i i
Versio
i
n
COM
IND
MIL
AUTO
IND
MIL
AUTO
1
10
20
200
80
90
45
55
IND
MIL
AUTO
1
10
20
200
70
80
40
50
Unit
i
Value
COM
COM
PRELIMINARY
I
CCSB (6)
I
CCSB1 (7)
I
CCOP (8)
I
CCOP1 (9)
Notes :
6.
7.
8.
9.
Standby supply current
(Both ports TTL level inputs)
Standby supply current
(Both ports CMOS level inputs)
Operating supply current
(Both ports active)
Operating supply current
(One port active – One port standby)
V
L
V
L
V
L
V
L
1
5
10
100
80
80
50
60
1
10
20
200
90
100
55
65
1
5
10
100
70
70
40
50
1
5
10
100
60
60
35
45
mA
mA
µA
µA
mA
mA
mA
mA
Max
Max
Max
Max
Max
Max
Max
Max
CS
L
= CS
R
≥
2.2 V.
CS
L
= CS
R
≥
VCC – 0.2 V.
Both ports active – Maximum frequency – Outputs open – OE = VIH.
One port active (f = MAX) – Output open – One port stand-by TTL or CMOS Level inputs – CS
L
= CS
R
≥
2.2 V.
PARAMETER
II/O
(10)
VIL
(11)
VIH
(11)
VOL
(12)
VOL
(13)
VOH
(12)
C IN
(17)
C OUT
(17)
Notes :
10.
11.
12.
13.
DESCRIPTION
Input/Output leakage current
Input low voltage
Input high voltage
Output low voltage (I/O
0
–I/O
7
)
Open drain output low voltage (BUSY)
Output high voltage
Input capacitance
Output capacitance
L67132–45/55/70
L67142–45/55/70
±
10
0.7
1.8
0.5
0.5
1.5
5
7
UNIT
µA
V
V
V
V
V
pF
pF
VALUE
Max
Max
Min
Max
Max
Min
Max
Max
V
CC
= 5 V, Vin = Gnd to V
CC
, CS = VIH, Vout = 0 to V
CC
.
VIH max = V
CC
+ 0.3 V, VIL min – 0.3 V or –1 V pulse width 50 ns.
V
CC
min, IOL = 4 mA, IOH = –4 mA.
I
OL
= 16 mA.
MATRA MHS
Rev. D (19 Fev. 97)
5
FPGA/CPLD
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