54F 74F373 Octal Transparent Latch with TRI-STATE Outputs
May 1995
54F 74F373
Octal Transparent Latch with TRI-STATE Outputs
General Description
The ’F373 consists of eight latches with TRI-STATE outputs
for bus organized system applications The flip-flops appear
transparent to the data when Latch Enable (LE) is HIGH
When LE is LOW the data that meets the setup times is
latched Data appears on the bus when the Output Enable
(OE) is LOW When OE is HIGH the bus output is in the high
impedance state
Features
Y
Y
Y
Eight latches in a single package
TRI-STATE outputs for bus interfacing
Guaranteed 4000V minimum ESD protection
Commercial
74F373PC
Military
Package
Number
N20A
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
54F373DM (QB)
74F373SC (Note 1)
74F373SJ (Note 1)
74F373MSA (Note 1)
54F373FM (QB)
54F373LM (QB)
J20A
M20B
M20D
MSA20
W20A
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX SJX and MSAX
Logic Symbols
IEEE IEC
O
C
1995 National Semiconductor Corporation
TL F 9523
bs
ol
Pin Assignment
for DIP SOIC SSOP and Flatpak
TL F 9523–4
TL F 9523 – 2
TL F 9523–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
RRD-B30M75 Printed in U S A
et
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Molded Shrink Small Outline EIAJ Type II
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
20-Lead (0 300 Wide) Molded Small Outline JEDEC
Connection Diagrams
Pin Assignment
for LCC
e
Package Description
TL F 9523 – 3
Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
Input I
IH
I
IL
Output I
OH
I
OL
20
mA
b
0 6 mA
20
mA
b
0 6 mA
20
mA
b
0 6 mA
b
3 mA 24 mA (20 mA)
D
0
– D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
TRI-STATE Latch Outputs
Functional Description
The ’F373 contains eight D-type latches with TRI-STATE
output buffers When the Latch Enable (LE) input is HIGH
data on the D
n
inputs enters the latches In this condition
the latches are transparent i e a latch output will change
state each time its D input changes When LE is LOW the
latches store the information that was present on the D in-
puts a setup time preceding the HIGH-to-LOW transition of
LE The TRI-STATE buffers are controlled by the Output
Enable (OE) input When OE is LOW the buffers are in the
bi-state mode When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches
Truth Table
Inputs
LE
H
H
L
X
OE
L
L
L
H
D
n
H
L
X
X
Output
O
n
H
L
O
n
(no change)
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance State
Logic Diagram
bs
ol
2
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
O
et
TL F 9523 – 5
e
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
b
65 C to
a
150 C
b
55 C to
a
125 C
b
55 C to
a
175 C
b
55 C to
a
150 C
b
0 5V to
a
7 0V
b
0 5V to
a
7 0V
b
30 mA to
a
5 0 mA
Voltage Applied to Output
in HIGH State (with V
CC
e
0V)
Standard Output
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
b
0 5V to V
CC
b
0 5V to
a
5 5V
twice the rated I
OL
(mA)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
b
55 C to
a
125 C
0 C to
a
70 C
a
4 5V to
a
5 5V
a
4 5V to
a
5 5V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% V
CC
54F 10% V
CC
74F 10% V
CC
74F 10% V
CC
74F 5% V
CC
74F 5% V
CC
54F 10% V
CC
74F 10% V
CC
20
08
54F 74F
Typ
Max
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
bs
ol
Output LOW
Voltage
05
05
V
Min
Input HIGH Current
54F
74F
20 0
50
100
70
mA
mA
mA
V
Max
Max
Max
00
00
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
54F
74F
54F
74F
74F
74F
250
50
Input Leakage
Test
4 75
Output Leakage
Circuit Current
3 75
mA
Input LOW Current
b
0 6
25
24
25
24
27
27
O
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
Output Leakage Current
Output Leakage Current
Bus Drainage Test
Power Supply Current
Output Short-Circuit Current
b
60
et
V
b
1 2
50
b
50
b
150
500
38
55
3
e
Units
V
V
CC
Conditions
V
Min
I
IN
e b
18 mA
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
e
e
e
e
e
e
b
1 mA
b
3 mA
b
1 mA
b
3 mA
b
1 mA
b
3 mA
Recognized as a HIGH Signal
Recognized as a LOW Signal
V
Min
I
OL
e
20 mA
I
OL
e
24 mA
V
IN
e
2 7V
V
IN
e
7 0V
V
OUT
e
V
CC
I
ID
e
1 9
mA
All Other Pins Grounded
V
IOD
e
150 mV
All Other Pins Grounded
V
IN
e
0 5V
V
OUT
e
2 7V
V
OUT
e
0 5V
V
OUT
e
0V
V
OUT
e
5 25V
V
O
e
HIGH Z
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
0 0V
Max
AC Electrical Characteristics
74F
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
Output Disable Time
30
20
50
30
20
20
15
15
T
A
e a
25 C
V
CC
e a
5 0V
C
L
e
50 pF
Typ
53
37
90
52
50
56
45
38
Max
70
50
11 5
70
11 0
75
65
50
54F
T
A
V
CC
e
Mil
C
L
e
50 pF
Min
30
20
50
30
20
20
15
15
Max
85
70
15 0
85
13 5
10 0
10 0
70
74F
T
A
V
CC
e
Com
C
L
e
50 pF
Min
30
20
50
30
20
20
15
15
Max
80
60
13 0
80
12 0
85
75
60
ns
ns
ns
ns
Units
AC Operating Requirements
74F
Symbol
Parameter
T
A
e a
25 C
V
CC
e a
5 0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
Setup Time HIGH or LOW
D
n
to LE
Hold Time HIGH or LOW
D
n
to LE
LE Pulse Width HIGH
20
20
30
30
Max
54F
bs
ol
60
60
60
74F
373
S
C
X
4
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
Temperature Range Family
74F
e
Commercial
54F
e
Military
Device Type
O
Package Code
P
e
Plastic DIP
D
e
Ceramic DIP
F
e
Flatpak
L
e
Leadless Chip Carrier (LCC)
S
e
Small Outline SOIC JEDEC
SJ
e
Small Outline SOIC EIAJ
MSA
e
Shrink Small Outline (EIAJ SSOP)
et
T
A
V
CC
e
Mil
T
A
V
CC
e
Com
Min
20
20
Max
Min
20
20
Max
30
40
30
30
Special Variations
QB
e
Military grade device with
environmental and burn-in
processing
X
e
Devices shipped in 13 reel
Temperature Range
C
e
Commercial (0 C to
a
70 C)
M
e
Military (
b
55 C to
a
125 C)
NOTE
Not required for MSA package code
e
74F
Units
ns
ns
Physical Dimensions
inches (millimeters)
O
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
5
bs
ol
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
et
e
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