DATASHEET
ISL9444
Triple, 180° Out-of-Phase, Synchronous Step-Down PWM Controller
The ISL9444 is a triple-output synchronous buck controller that
integrates three PWM controllers which are fully featured and
designed to provide multi-rail power for use in products such as
cable and satellite set-top boxes, VoIP gateways, cable modems,
and other home connectivity products as well as a variety of
industrial and general purpose applications. Each output is
adjustable down to 0.7V. The PWMs are synchronized at 180°
out-of-phase, thus reducing the input RMS current and ripple
voltage.
The ISL9444 offers independent power-good indicators,
programmable soft-start and tracking functions for ease of
supply rail sequencing and integrated UV/OV/OC/OT
protections in a space conscious 5mmx5mm QFN package.
Switching frequency can be set between 200kHz and 1200kHz
using a resistor. The ISL9444 can be synchronized to another
ISL9444 to reduce any beat frequency.
The ISL9444 utilizes internal loop compensation to keep
minimum peripheral components for a compact design and a
low total solution cost. These devices are implemented with
current mode control with feed-forward to cover various
applications even with fixed internal compensations.
FN7665
Rev 3.00
May 29, 2012
Features
• Three Integrated Synchronous Buck PWM Controllers
- Internal Bootstrap Diodes
- Independent Programmable Output Voltage
- Independent Power-Good Indicators, Soft-Starting and
Tracking
• Power Failure Monitor
• Light Load Efficiency Enhancement
- Low Ripple Diode Emulation Mode with Pulse Skipping
• Supports Pre-Biased Output
• Programmable Frequency: 200kHz to 1200kHz
• Adaptive Shoot-through Protection
• Out-of-Phase Switching (0°/180°/0°)
• No External Current Sense Resistor
- Uses Lower MOSFET’s r
DS(ON)
• Complete Protection
- Overcurrent, Overvoltage, Over-Temperature
• Wide Input Voltage Range: 4.5V to 28V
• Pb-Free (RoHS Compliant)
Related Literature
• Technical Brief
TB389
“PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages”
Applications
• VoX Gateway Devices
• NAS/SAN Devices
• ATX Power Supplies
+12V
+
CIN1
CIN2
Q1
Q2
L2 2.2µH
0.1µF
0.1µF
CB2
PHASE2
UGATE1
UGATE2
LGATE2
BOOT1
BOOT2
PGND
ISEN2
FB2
+12V
UGATE3
RESN2
1.3kΩ
R9
11.5kΩ
VOUT2
+3.3V, 6A
+
CO2
100µF
VOUT1
+1.0V, 6A
CO1
100µF
+
L1
1.0µH
ISEN1
+12V
R2
62kΩ
C1
4.7µF
VIN
VCC_5V
EXTBIAS
PFI
R1
10kΩ
PFO
EN2,3
PHASE1
LGATE1
RESN1
1.3kΩ
CB1
R8
3.09kΩ
R4
15.8kΩ
ISL9444
MODE/SYNC
CLKOUT
PGOOD1,2,3
TK/SS2,3
BOOT3
PHASE3
CB3
0.1µF
Q3
L3 3.3µH
VOUT3
+5.0V, 6A
+
CO3
100µF
FB1
OCSET1
OCSET2
SGND
R3
31.6kΩ
RT
RT
49.9kΩ
EN/SS1
CSS
10nF
OCSET2
LGATE3
FB3
ISEN3
RESN3
1.3kΩ
R4
10.7kΩ
R3
1.74kΩ
R5
100kΩ
R6
200kΩ
R7
200kΩ
FIGURE 1. TYPICAL APPLICATION
FN7665 Rev 3.00
May 29, 2012
Page 1 of 25
ISL9444
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL9444IRZ
ISL9444CRZ
ISL9444EVAL1Z
NOTES:
1. Add “-T*” for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL9444.
For more information on MSL please see techbrief
TB363.
PART
MARKING
ISL9444 IRZ
ISL9444 CRZ
Evaluation Board
TEMP. RANGE
(°C)
-40 to +85
-0 to +85
PACKAGE
(Pb-Free)
40 Ld 5x5 QFN
40 Ld 5x5 QFN
PKG.
DWG. #
L40.5X5B
L40.5X5B
Pin Configuration
ISL9444
(40 LD 5x5 QFN)
TOP VIEW
PHASE1
PHASE2
UGATE1
UGATE2
LGATE1
LGATE2
BOOT1
BOOT2
ISEN1
ISEN2
30 CLKOUT
29 PGND
28 LGATE3
27 UGATE3
26 BOOT3
25 PHASE3
24 ISEN3
23 MODE/SYNC
22 EN3
21 TK/SS3
11 12 13 14 15 16 17 18 19 20
OCSTET3
PGOOD2
PGOOD3
OCSET2
SGND
FB2
PG3_DLY
EN2
TK/SS2
FB3
40 39 38 37 36 35 34 33 32 31
PFO 1
PFI 2
EXTBIAS 3
VCC_5V 4
VIN 5
EN/SS1 6
FB1 7
OCSET1 8
RT 9
PGOOD1 10
Pin Descriptions
PIN
1
2
3
NAME
PFO
PFI
EXTBIAS
FUNCTION
Output of the auxiliary power monitor. PFO goes high if the voltage on PFI is greater than 1.2V (typical). Otherwise the
PFO outputs low.
Input to the auxiliary power monitor. The internal threshold voltage is 1.2V (typical).
Input from an optional external 5V bias supply. There is an internal switch from this pin to VCC_5V. This switch closes and
supplies the IC power, bypassing the internal linear regulator, when voltage at EXTBIAS is higher than 4.7V (typ). Do not
allow voltage at the EXTBIAS pin to exceed VIN at any time.
Decouple this pin to ground with a small ceramic capacitor (0.1µF to 1µF) when it is in use, otherwise tie this pin to
ground. Do not float this pin.
Output of the internal 5V linear regulator. This output supplies bias for the IC, the low side gate drivers, and the external
boot circuitry for the high-side gate drivers. The VCC_5V pin must be always decoupled to power ground with a minimum
of 4.7µF ceramic capacitor, placed very close to the pin. Do not allow the voltage at VCC_5V to exceed VIN at any time.
4
VCC_5V
FN7665 Rev 3.00
May 29, 2012
Page 2 of 25
ISL9444
Pin Descriptions
(Continued)
PIN
5
NAME
VIN
FUNCTION
This pin should be tied to the input rail. It provides power to the internal linear drive circuitry and is also used by the
feed-forward controller to adjust the amplitude of each PWM sawtooth. Decouple this pin with a small ceramic capacitor
(0.1µF to 1µF) to ground.
This pin provides an enable/disable function and soft-starting for PWM1 output. The output is disabled when the pin is
pulled to GND. During start-up, a regulated 1.55µA soft-start current charges an external capacitor connected at this pin.
When the voltage on the EN/SS1 pin reaches 1.3V, the PWM1 output becomes active. From 1.3V to 2.0V, the reference
voltage of the PWM1 is clamped to the voltage at EN/SS1 minus 1.3V. The capacitance of the soft-start capacitors sets
the soft-starting time and enable delay time. Setting the soft-starting time too short might create undesirable overshoot
at the output during start-up. VCC_5V UVLO discharges the EN/SS1 via an internal MOSFET.
PWM1 feedback input. Connect FB1 to a resistive voltage divider from the output of PWM1 to GND to adjust the output
voltage.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM1.
A resistor from this pin to ground adjusts the switching frequency from 200kHz to 1.2MHz. The switching frequency of
the PWM controller is determined by the resistor, R
T
,
R
T
=
23.36
1.5
t
SW
–
0.36
k
where t
SW
is the switching period in µs.
10
11
12
13
14
15
PGOOD1
PGOOD2
PGOOD3
PG3_DLY
EN2
SGND
Open drain logic output used to indicate the status of the PWM1 output voltage. This pin is pulled down when the PWM1
output is not within ±11% of the nominal voltage.
Open drain logic output used to indicate the status of the PWM2 output voltage. This pin is pulled down when the PWM2
output is not within ±11% of the nominal voltage.
Open drain logic output used to indicate the status of the PWM3 output voltage. This pin is pulled down when the PWM3
output is not within ±11% of the nominal voltage.
A capacitor connected between this pin and ground sets a delay between PWM3 output voltage reaching ±11% of
regulation and PGOOD3 going high. There is no delay when PWM3 goes out of regulation and PGOOD3 is pulled low.
Enable/Disable input for PWM2. The output of PWM2 is enabled when this pin is pulled HIGH, and disabled when this pin
is pulled LOW. PGOOD2 is pulled LOW 1µs after EN2 is pulled LOW. Do not leave this pin floating.
This is the small-signal ground common to all 3 controllers. It is suggested to route this separately from the high current
ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around the
chip. All voltage levels are measured with respect to this pin.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM2.
PWM2 feedback input. Connect FB2 to a resistive voltage divider from the output of PWM2 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM2 is clamped to the voltage at TK/SS2 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM2 output voltage ramp.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM3.
PWM3 feedback input. Connect FB3 to a resistive voltage divider from the output of PWM3 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM3 is clamped to the voltage at TK/SS3 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM3 output voltage ramp.
Enable/Disable input for PWM3. The output of PWM3 is enabled when this pin is pulled HIGH, and disabled when this pin
is pulled LOW. PGOOD3 is pulled LOW 1µs after EN3 is pulled LOW. Do not leave this pin floating.
(EQ. 1)
6
EN/SS1
7
8
9
FB1
OCSET1
RT
16
17
18
OCSET2
FB2
TK/SS2
19
20
21
OCSET3
FB3
TK/SS3
22
EN3
FN7665 Rev 3.00
May 29, 2012
Page 3 of 25
ISL9444
Pin Descriptions
(Continued)
PIN
23
NAME
MODE/SYNC
FUNCTION
Dual function pin. Tie this pin to ground or VCC_5V for DEM or CCM operation mode selection. Connect this pin to ground
to select Diode Emulation Mode with pulse skipping at light load. While connected to VCC_5V, the controllers operate in
PWM Mode at light load.
Connect this pin to CLKOUT of another ISL9444 or an external clock for synchronization. The controller operates in PWM
at light load when synchronized with another ISL9444 or with an external clock.
Current signal input for PWM3. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM3. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE3 is the internal lower supply rail for the UGATE3.
Bootstrap pin to provide bias for PWM3 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM3.
Low-side MOSFET gate driver output for PWM3.
Power ground connection for all three PWM channels. This pin should be connected to the sources of the lower MOSFETs
and the (-) terminals of the external input capacitors
Clock signal output. The frequency of the clock signal is two times of the ISL9444 switching frequency set by the resistor
from RT to ground.
Current signal input for PWM2. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
Phase node connection for PWM2. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE2 is the internal lower supply rail for the UGATE2.
Bootstrap pin to provide bias for PWM2 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
High-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM2.
Low-side MOSFET gate driver output for PWM1.
High-side MOSFET gate driver output for PWM1.
Bootstrap pin to provide bias for PWM1 high-side driver. The positive terminal of the bootstrap capacitor connects to this
pin. The bootstrap diodes are integrated to help reduce total cost and reduce layout complexity.
Phase node connection for PWM1. This pin is connected to the junction of the upper MOSFET’s source, output filter inductor,
and lower MOSFET’s drain. PHASE1 is the internal lower supply rail for the UGATE1.
Current signal input for PWM1. This pin is used to monitor the voltage drop across the lower MOSFET for current loop
feedback and overcurrent protection.
EPAD at ground potential. Solder it directly to GND plane for better thermal performance.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
-
ISEN3
PHASE3
BOOT3
UGATE3
LGATE3
PGND
CLKOUT
ISEN2
PHASE2
BOOT2
UGATE2
LGATE2
LGATE1
UGATE1
BOOT1
PHASE1
ISEN1
EPAD
FN7665 Rev 3.00
May 29, 2012
Page 4 of 25
Block Diagram
BOOT1
VCC_5V
UGATE1
PHASE1
ADAPTIVE DEAD-TIME
VCC_5V
LGATE1
PGND
POR
PGND
PFI
PF REF
PFO
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
(see Note 6)
EN/SS1
EN2
EN3
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
FB1
180kΩ
1000kΩ
15pF
VCC_5V
LGATE3
VCC_5V
UGATE3
PHASE3
PGND
BOOT3
V/I SAMPLE TIMING
2µA
PGOOD1 PGOOD2 PGOOD3 PG3_DLY VIN VCC_5V
EXTBIAS
VCC_5V
UGATE2
PHASE2
BOOT2
CLKOUT
MODE/SYNC
RT
FN7665 Rev 3.00
May 29, 2012
Page 5 of 25
ISL9444
+
_
SW THRES.
ADAPTIVE DEAD-TIME
V/I SAMPLE TIMING
VCC_5V
LGATE2
+
_
_
180kΩ
+ 0.7V
REF
ERROR AMP 1
1.55µA
EN/SS1
1.3V
ISEN1
CURRENT
SAMPLE
OCSET1
VIN
VCC_5V
MINIMUM
SOFT-START
ISEN3
OCSET3
OCP
+
16kΩ
PGND
_
_
+
FB1 FB2 FB3
OC3
ERROR AMP 3
PWM1
OC1 OC2 OC3
OV
PWM3
FB3
0.7V REF
TK/SS3
+
EN/SS1
+
EN3
_
+
+
CURRENT
SAMPLE
DUTY CYCLE RAMP GENERATOR
CHANNEL 3
PWM CHANNEL PHASE CONTROL
PWM2
FB2
TK/SS2
EN3
ISEN2
OC2
OCSET2
1.75V REFERENCE
-
+
OC1
SAME STATE FOR
2
CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
CHANNEL 1
CHANNEL 2
SGND
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