TS68302
Integrated Multiprotocol Processor (IMP)
Datasheet
Features
•
TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family
•
System Integration Block Including:
Independent Direct Memory Access (IDMA) Controller
Interrupt Controller with Two Modes of Operation
Parallel Input/output (I/O) Ports, some with Interrupt Capability
On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
Three Timers, including a Watchdog Timer
Four Programmable Chip-select Lines with Wait-state Logic
Programmable Address Mapping of Dual-port RAM and IMP Registers
On-chip Clock Generator with an Output Clock Signal
System Control:
• System Control Register
• Bus Arbitration Logic with Low Interrupt Latency Support
• Hardware Watchdog for Monitoring Bus Activity
• Low Power (Standby) Modes
• Disable CPU Logic (TS68000)
• Freeze Control for Debugging Selected On-chip Peripherals
• DRAM Refresh Controller
•
Communications Processor Including:
– Main Controller (RISC Processor)
– Three Full-duplex Serial Communication Controllers (SCCs)
– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL) General Circuit Interface (GCI, see note),
Pulse Code Modulation (PCM), and Nonmultiplexed Serial Interface (NMSI) Operation
– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up to 4.096 MHz
– Serial Management Controllers (SMCs) for IDL and GCI Channels
•
Frequency of Operation: 16.67 MHz
•
Power Supply: 5 V
DC
± 10%
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e2v semiconductors SAS 2008
0855B–HIREL–04/08
TS68302
Description
The IMP is a very large-scale integration (VLSI) device incorporating the main building blocks needed for
the design of a wide variety of controllers. The device is especially suitable to applications in the commu-
nications industry. The IMP is the first device to offer the benefits of a closely coupled, industry-standard,
TS68000/TS68008 microprocessor core and a flexible communications architecture. This multichannel
communications device may be configured to support a number of popular industry interfaces, including
those for the integrated services digital network (ISDN) basic rate and terminal adapter applications.
Through a combination of architectural and programmable features, concurrent operation of different
protocols is easily achieved using the IMP. Data concentrators, line cards, bridges, and gateways are
examples of suitable applications for this versatile device.
The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of a
TS68000/TS68008 microprocessor core, a system integration block (SIB), and a communications pro-
cessor (CP). The TS68302 block diagram is shown in
Figure 1-1.
GCI is sometimes referred to as IOM2.
Screening/Quality
This product is manufactured in full compliance with either:
• MIL-STD-883 (class B)
• DESC. Drawing 5962-93159
• Or according to e2v standards
A suffix
CERQUAD 132
(Ceramic Quad Flat Pack)
R suffix
PGA 132
(Ceramic Pin Grid Array)
1. Introduction
The TS68302 integrated multiprotocol processor (IMP) is a very large-scale integration (VLSI) device
incorporating the main building blocks needed for the design of a wide variety of controllers. The device
is especially suitable to applications in the communications industry. The IMP is the first device to offer
the benefits of a closely coupled, industry-standard TS68000 microprocessor core and a flexible commu-
nications architecture. The IMP may be configured to support a number of popular industry interfaces,
including those for the Integrated Services Digital Network (ISDN) basic rate and terminal adapter appli-
cations. Concurrent operation of different protocols is easily achieved through a combination of
architectural and programmable features. Data concentrators, line cards, bridges, and gateways are
examples of suitable applications for this device.
2
0855B–HIREL–04/08
e2v semiconductors SAS 2008
TS68302
The IMP is a high-density complementary metal-oxide semiconductor (HCMOS) device consisting of a
TS68000 microprocessor core, a system integration block (SIB), and a communications processor (CP).
Figure 1-1
is a block diagram of the TS68302. The processor can be divided into two main sections: the
bus controller and the micromachine. This division reflects the autonomy with which the sections
operate.
Figure 1-1.
TS68302 Block Diagram
TS68000/TS68008 CORE
TS68000 BUS
TS68000/TS68008 CORE
ON-CHIP PERIPHERALS BUS INTERFACE UNIT
INTERRUPT
CONTROLLER
BUS ARBITER
1152 BYTES
DUAL-PORT
STATIC RAM
CHIP-SELECT
AND WAIT-
STATE LOGIC
SYSTEM
CONTROL
IDMA
(1 CHANNEL)
TIMERS (3)
CLOCK
GENERATOR
DRAM
REFRESH
CONTROLLER
PARALLEL I/O
SYSTEM INTEGRATION BLOCK
PERIPHERAL BUS
SDMA
(6 CHANNELS)
SMC (2)
SCC1
SCC2
SCC3
SCP
MAIN
CONTROLLER
(RISC)
SERIAL CHANNELS PHYSICAL INTERFACE
COMMUNICATIONS PROCESSOR
I/O PORTS AND PIN ASSIGNEMENTS
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TS68302
2. Pin Assignments
Figure 2-1.
PGA Terminal Designation
N
PB10
TIN1 IACK1 GND UDS
R/W EXTAL VDD
IPL1 IPL2 RESET HALT RCLK1
M
CS3 TOUT2 TIN2 VDD IACK7
AS
GND CLK0 BERR BR BGACK
BG
AVEC NC1
RTS3
L
CS2 PB11
GND TOUT1 IACK6 LDS XTAL IPL0
IAC
PB9 WDOG
PB8
BCLR TCLK1 CD3
K
CS0
RMC
DTACK VDD TXD1 RTS1 BUSW
GND BRG1 NC3 DISCPU
J
H
G
F
E
D
C
B
A
FC2
CS1
GND
VDD
A3
A4
A8
GND
A13
A18
A21
FC0
A1
GND
A6
A7
A10
A11
A14
FC1
A2
A5
A9
A12
VDD
TS68302
BOTTOM VIEW
FRZ DONE DACK
PA12 DREQ GND
TXD3 RCLK3 TCLK3
TXD2 CD2 SDS2 RXD3
A15
GND
A20
A16
A23
VDD
D14
D13
D11 VDD
D10
D8
D9
RXD2 CTS1 TCLK2 GND
D4
D5
D7
D1
D2
D6
VDD
A17
A19
A22
CD1 RCLK2 RTS2
D0
GND
CTS3 CTS2
D3
RXD1
GND D15
D12 GND
1
2
3
4
5
6
7
8
9
10
11
12
13
4
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e2v semiconductors SAS 2008
TS68302
Figure 2-2.
CERQUAD Terminal Designation
VDD
A16
A17
A18
A19
GND
A20
A21
A22
A23
VDD
GND
D15
D14
D13
D12
GND
D11
D10
D9
D8
VDD
D7
D6
D5
D4
GND
D3
D2
D1
D0
CTS3
CD1
A15
A14
A13
A12
GND
A11
A10
A9
A8
A7
A6
A5
A4
GND
A3
A2
A1
FC0
VDD
FC1
FC2
CS0
CS1
GND
CS2
CS3
RMC
IAC
PB11
PB10
PB9
PB8
WDOG
17
1
117
68302
CERQUAD132
(window frame down)
Top VIEW
50
83
GND
TOUT2
TIN2
TOUT1
VDD
TIN1
IACK1
IACK6
IACK7
GND
UDS
LDS
AS
R/W
GND
XTAL
EXTAL
VDD
CLK0
IPL0
IPL1
IPL2
BERR
AVEC
RESET
HALT
BR
NC1
BGACK
BG
BCLR
DTACK
GND
CTS1
RXD1
RXD2
TXD2
RCLK2
TCLK2
GND
CTS2
RTS2
CD2
SDS2
VDD
RXD3
TXD3
RCLK3
TCLK3
GND
PA12
DREQ
DACK
DONE
FRZ
DISCPU
BUSW
NC3
BRG1
CD3
RTS3
RTS1
TXD1
TCLK1
RCLK1
VDD
5
0855B–HIREL–04/08
e2v semiconductors SAS 2008
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