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54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
June 1989
54LS42 DM54LS42 DM74LS42 BCD Decimal Decoders
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten four-input NAND gates The inverters are connect-
ed in pairs to make BCD input data available for decoding
by the NAND gates Full decoding of input logic ensures
that all outputs remain off for all invalid (10–15) input condi-
tions
Features
Y
Y
Y
Y
Diode clamped inputs
Also for applications as 4-line-to-16-line decoders 3-
line-to-8-line decoders
All outputs are high for invalid input conditions
Alternate Military Aerospace device (54LS42) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
No
0
1
2
3
4
5
6
7
8
9
I
N
V
A
L
I
D
BCD Inputs
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
1
H
L
H
H
H
2
Decimal Outputs
3
4
5
6
7
8
9
H H H H H H H H
H H H H H H H H
L H H H H H H H
H L H H H H H H
H H L H H H H H
H H H L H H H H
H H H H L H H H
H H H H H L H H
H H H H H H L H
H H H H H H H L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
H H
TL F 6365 – 1
Order Number 54LS42DMQB 54LS42FMQB
DM54LS42J DM54LS42W DM74LS42M or DM74LS42N
See NS Package Number J16A M16A N16E or W16A
H
e
High Level
L
e
Low Level
Logic Diagram
TL F 6365 – 2
C
1995 National Semiconductor Corporation
TL F 6365
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
Input Voltage
7V
7V
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Operating Free Air Temperature Range
b
55 C to
a
125 C
DM54LS and 54LS
DM74LS
0 C to
a
70 C
Storage Temperature Range
b
65 C to
a
150 C
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Parameter
Min
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
b
55
DM54LS42
Nom
5
Max
55
Min
4 75
2
07
b
0 4
DM74LS42
Nom
5
Max
5 25
Units
V
V
08
b
0 4
45
2
V
mA
mA
C
4
125
0
8
70
Electrical Characteristics
Symbol
V
I
V
OH
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
over recommended operating free air temperature range (unless otherwise noted)
Conditions
V
CC
e
Min I
I
e b
18 mA
V
CC
e
Min I
OH
e
Max
V
IL
e
Max V
IH
e
Min
V
CC
e
Min I
OL
e
Max
V
IL
e
Max V
IH
e
Min
I
OL
e
4 mA V
CC
e
Min
DM54
DM74
DM54
DM74
DM74
25
27
34
34
0 25
0 35
0 25
04
05
04
01
20
b
0 4
Min
Typ
(Note 1)
Max
b
1 5
Units
V
V
V
OL
V
I
I
I
IH
I
IL
I
OS
Input Current
Input Voltage
Max
V
CC
e
Max V
I
e
7V
V
CC
e
Max V
I
e
2 7V
V
CC
e
Max V
I
e
0 4V
V
CC
e
Max
(Note 2)
V
CC
e
Max (Note 3)
DM54
DM74
b
20
b
20
mA
mA
mA
mA
mA
High Level Input Current
Low Level Input Current
Short Circuit
Output Current
Supply Current
b
100
b
100
I
CC
7
13
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3
I
CC
is measured with all outputs open and all inputs grounded
2
Switching Characteristics
Symbol
Parameter
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
R
L
e
2 kX
From (Input)
To (Output)
A B C or D (2 Levels
of Logic) to Output
A B C or D (3 Levels
of Logic) to Output
A B C or D (2 Levels
of Logic) to Output
A B C or D (3 Levels
of Logic) to Output
C
L
e
15 pF
Min
Max
25
30
25
30
C
L
e
50 pF
Min
Max
30
35
30
35
ns
ns
ns
ns
Units
t
PHL
t
PHL
t
PLH
t
PLH
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
Low to High Level Output
3
Physical Dimensions
inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS42DMQB or DM54LS42J
NS Package Number J16A
4
FPGA/CPLD
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