June 2008
HYS72T[64/128/256]xx0EP–[2.5/25F]–B2
HYS72T[64/128/256]xx0EP–[3/3S]–B2
HYS72T[64/128/256]xx0EP–3.7–B2
240-Pin Registered DDR2 SDRAM Modules
RDIMM SDRAM
EU RoHS Compliant
Internet Data Sheet
Rev. 1.02
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
HYS72T[64/128/256]xx0EP–[2.5/25F]–B2, HYS72T[64/128/256]xx0EP–[3/3S]–B2, HYS72T[64/128/256]xx0EP–3.7–B2
Revision History: 2008-06, Rev. 1.02
Page
All
All
All
Subjects (major changes since last revision)
Editorial change and adapted to internet edition.
Editorial change.
Final document.
Previous Revision: 2008-01, Rev. 1.01
Previous Revision: 2007-07, Rev. 1.0
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Your feedback will help us to continuously improve the quality of this document.
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
07312007-HYD2-P177
2
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM modules product family with parity bit for address and
control bus and describes its main characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh.
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
μs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
Serial Presence Detect with E
2
PROM.
Dimensions (nominal): 30 mm high, 133.35 mm wide
Based on standard reference layouts Raw Cards 'F', 'L', 'G'
and 'H'.
RoHS compliant products
1)
.
• 240-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2
SDRAM memory modules.
• One rank 128M
×
72, 64M
×
72 and , two rank 128M
×
72,
256M
×
72 module organization, and 64M
×
8, 128M
×
4
chip organization.
• 2GB, 1GB, 512MB Modules built with 512MBit DDR2
SDRAMs in chipsize packages PG-TFBGA-60.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5, 6 and 7 ), Burst
Length (8 & 4).
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Active Time
Min. Row Cycle Time
DDR2
PC2
–25F
–800D
–6400D
5–5–5
–2.5
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
40
60
–3
–667C
–5300C
4–4–4
200
333
333
–
12
12
45
40
57
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
40
60
–3.7
–533C
–4200C
4–4–4
200
266
266
–
15
15
45
40
60
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
1)
2)
1)
Unit
Note
t
CK
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RAS
t
RC
200
266
400
–
12.5
12.5
45
40
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products
.
Rev. 1.02, 2008-06
07312007-HYD2-P177
3
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
DDR2
PC2
–25F
–800D
–6400D
5–5–5
52.5
12.5
–2.5
–800E
–6400E
6–6–6
55
15
–3
–667C
–5300C
4–4–4
52
12
–3S
–667D
–5300D
5–5–5
55
15
–3.7
–533C
–4200C
4–4–4
55
15
Unit
Note
t
CK
t
RC
Precharge-All (4 banks) command
t
PREA
Min. Row Cycle Time
period
ns
ns
2)
1) Product released after 2007-08-01 will support
t
RAS
= 40 ns for all DDR2 speed sort.
2) For products after 2007-08-01.
1.2
Description
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E
2
PROM device using the 2-pin I
2
C
protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
The
Qimonda
HYS72T[64/128/256]xx0EP–
[2.5/25F/3/3S/3.7]–B2 module family are Registered DIMM
modules “RDIMMs” with parity bit for address and control bus
and 30 mm height based on DDR2 technology. DIMMs are
available as ECC modules
in 128M
×
72 (1GB),
256M
×
72 (2GB), 64M
×
72 (512MB) in organization and
density, intended for mounting into 240-pin connector
sockets.
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (5-5-5)
HYS72T256220EP-25F-B2
HYS72T128020EP-25F-B2
HYS72T128000EP-25F-B2
HYS72T64000EP-25F-B2
PC2-6400 (6-6-6)
HYS72T256220EP-2.5-B2
HYS72T128020EP-2.5-B2
HYS72T128000EP-2.5-B2
HYS72T64000EP-2.5-B2
2GB 2R×4 PC2–6400P–666–12–L0
1GB 2R×8 PC2–6400P–666–12–G0
1GB 1R×4 PC2–6400P–666–12–H0
512MB 1R×8 PC2–6400P–666–12–F0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
2GB 2R×4 PC2–6400P–555–12–L0
1GB 2R×8 PC2–6400P–555–12–G0
1GB 1R×4 PC2–6400P–555–12–H0
512MB 1R×8 PC2–6400P–555–12–F0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
Compliance Code
2)
Description
SDRAM Technology
Rev. 1.02, 2008-06
07312007-HYD2-P177
4
Internet Data Sheet
HYS72T[64/128/256]xx0EP–[2.5/25F/3/3S/3.7]–B2
Registered DDR2 SDRAM Modules
Product Type
1)
PC2-5300 (4-4-4)
HYS72T256220EP-3-B2
HYS72T128020EP-3-B2
HYS72T128000EP-3-B2
HYS72T64000EP-3-B2
PC2-5300 (5-5-5)
HYS72T256220EP-3S-B2
HYS72T128020EP-3S-B2
HYS72T128000EP-3S-B2
HYS72T64000EP-3S-B2
PC2-4200 (4-4-4)
HYS72T256220EP-3.7-B2
HYS72T128020EP-3.7-B2
HYS72T128000EP-3.7-B2
HYS72T64000EP-3.7-B2
Compliance Code
2)
Description
SDRAM Technology
2GB 2R×4 PC2–5300P–444–12–L0
1GB 2R×8 PC2–5300P–444–12–G0
1GB 1R×4 PC2–5300P–444–12–H0
512MB 1R×8 PC2–5300P–444–12–F0
2GB 2R×4 PC2–5300P–555–12–L0
1GB 2R×8 PC2–5300P–555–12–G0
1GB 1R×4 PC2–5300P–555–12–H0
512MB 1R×8 PC2–5300P–555–12–F0
2GB 2R×4 PC2–4200P–444–12–L0
1GB 2R×8 PC2–4200P–444–12–G0
1GB 1R×4 PC2–4200P–444–12–H0
512MB 1R×8 PC2–4200P–444–12–F0
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
2 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1 Rank, ECC
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
512Mbit (×4)
512Mbit (×8)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–F0" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and
produced on the Raw Card "F".
TABLE 3
Address Format
DIMM
Density
2GB
1GB
1GB
512MB
Module
Organization
256M
×
72
128M
×
72
128M
×
72
64M
×
72
Memory
Ranks
2
2
1
1
ECC/
Non-ECC
ECC
ECC
ECC
ECC
# of SDRAMs # of row/bank/column
bits
36
18
18
9
14/2/11
14/2/10
14/2/11
14/2/10
Raw
Card
L
G
H
F
TABLE 4
Components on Modules
Product Type
1)2)
HYS72T256220EP
HYS72T128020EP
HYS72T128000EP
HYS72T64000EP
DRAM Components
1)
HYB18T512400B2F
HYB18T512800B2F
HYB18T512400B2F
HYB18T512800B2F
DRAM Density
512Mbit
512Mbit
512Mbit
512Mbit
DRAM Organisation
128M
×
4
64M
×
8
128M
×
4
64M
×
8
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.02, 2008-06
07312007-HYD2-P177
5
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