ADVANCE INFORMATION
Am54BDS128AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s
Power supply voltage of 1.65 to 1.95 volt
s
High performance
— Access time as fast as 70 ns/ 54 Mhz Burst
s
Package
— 93-Ball FBGA
s
Operating Temperature
— –40°C to +85°C
s
Power dissipation (typical values, C
L
= 30 pF)
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.4 µA
Hardware features
s
Software command sector locking
s
Handshaking: host monitors operations via RDY
output
s
Hardware reset input (RESET#)
s
WP# input
— Write protect (WP#) function protects sectors 0, 1
(bottom boot) or sectors 132 and 133 (top boot),
regardless of sector protect status
s
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC = V
IL
s
CMOS compatible inputs, CMOS compatible outputs
s
Low V
CC
write inhibit
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s
Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
s
Manufactured on 0.17 µm process technology
s
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
s
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
s
Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
— Banks A and D each contain four 8 Kword sectors
and thirty-one 32 Kword sectors; Banks B and C
each contain thirty-two 32 Kword sectors
— Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
s
Minimum 1 million erase cycle guarantee per sector
s
20-year data retention at 125°C
SOFTWARE FEATURES
s
Supports Common Flash Memory Interface (CFI)
s
Software command set compatible with JEDEC 42.4
standards
s
Data# Polling and toggle bits
s
Erase Suspend/Resume
— Suspends or resumes an erase operation in one
sector to read data from, or program data to, other
sectors
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
SRAM Features
s
Power dissipation
— Operating: 3 mA maximum
— Standby: 15 µA maximum
s
s
s
s
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.0 to 2.2 volt
Byte data control: LB#s (DQ7–DQ0), UB#s
(DQ15–DQ8)
Publication#
26628
Rev:
A
Amendment/+1
Issue Date: July 23, 2002
PERFORMANCE CHARCTERISTICS
s
Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
— Asynchronous random access times of 70 ns (at 30
pF)
— Synchronous latency of 87.5/95 ns
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you
evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work
on this proposed product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device, orga-
nized as 4,194,304 words of 16 bits each. This device uses
a single V
CC
of 1.65 to 1.95 V to read, program, and erase
the memory array. A 12.0-volt V
ID
may be used for faster pro-
gram performance if desired. The device can also be pro-
grammed in standard EPROM programmers.
At 54 MHz, the device provides a burst access of 13.5 ns at
30 pF with a latency of 87.5 ns at 30 pF. At 40 MHz, the de-
vice provides a burst access of 20 ns at 30 pF with a latency
of 95 ns at 30 pF. The device operates within the industrial
temperature range of -40°C to +85°C. The device is offered
in a 93-ball FBGA package.
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into four
banks. The device can improve overall system performance
by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another
bank, with zero latency. This releases the system from wait-
ing for the completion of program or erase operations.
The device is divided as shown in the following table:
Bank
A
B
C
D
Quantity
4
31
32
32
31
4
Size
8 Kwords
32 Kwords
32 Kwords
32 Kwords
32 Kwords
8 Kwords
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
The
Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read boot-up firm-
ware from the Flash memory device.
The host system can detect whether a program or erase op-
eration is complete by using the device status bit DQ7
(Data# Polling) and DQ6/DQ2 (toggle bits). After a program
or erase cycle has been completed, the device automatically
returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The device also offers two types of data
protection at the sector level. The
sector lock/unlock com-
mand sequence
disables or re-enables both program and
erase operations in any sector. When at V
IL
,
WP#
locks sec-
tors 0 and 1 (bottom boot device) or sectors 132 and 133
(top boot device).
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power con-
sumption is greatly reduced in both modes.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunnelling. The data is programmed using
hot electron injection.
The device uses Chip Enable (CE#), Write Enable (WE#),
Address Valid (AVD#) and Output Enable (OE#) to control
asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and
Clock (CLK). This implementation allows easy interface with
minimal glue logic to a wide range of microprocessors/micro-
controllers for high performance read operations.
The burst read mode feature gives system designers flexibil-
ity in the interface to the device. The user can preset the
burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a
choice of active clock edges, either rising or falling. The ac-
tive clock edge initiates burst accesses and determines
when data will be output.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
July 23, 2002
Am54BDS128AG
2
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 7
Flash Memory Simultaneous Operation Diagram 8
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Package Handling Instructions .................................... 9
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11
MCP Device Bus Operations. . . . . . . . . . . . . . . . 11
Flash Device Bus Operations . . . . . . . . . . . . . . . 13
Requirements for Asynchronous Read
Operation (Non-Burst) ............................................................ 13
Requirements for Synchronous (Burst) Read Operation ........ 13
Table 2. Burst Address Groups .......................................................13
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 2. Write Operation Status ..................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 6. Maximum Negative Overshoot Waveform ...................... 35
Figure 7. Maximum Positive Overshoot Waveform........................ 35
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . .
Flash DC Characteristics . . . . . . . . . . . . . . . . . .
SRAM DC and Operating Characteristics . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .
35
36
37
38
Figure 8. Test Setup....................................................................... 38
Table 8. Test Specifications ........................................................... 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 9. Input Waveforms and Measurement Levels ................... 38
Burst Mode Configuration Register ........................................ 14
Handshaking Option ............................................................... 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Writing Commands/Command Sequences ............................ 14
Standby Mode ........................................................................ 15
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Input ............................................. 15
Output Disable Mode .............................................................. 15
Hardware Data Protection ...................................................... 15
Common Flash Memory Interface (CFI) . . . . . . . 16
Table 1. CFI Query Identification String ..........................................16
Table 2. System Interface String..................................................... 17
Table 3. Am29BDS640G Sector Address Table .............................19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
SRAM CE#s Timing ................................................................ 39
Figure 10. Timing Diagram for Alternating
Between SRAM and Flash ............................................................. 39
Synchronous/Burst Read ........................................................ 40
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK)..........................................................................
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock) .....................................................................
Figure 13. Synchronous Burst Mode Read ....................................
Figure 14. 8-word Linear Burst with Wrap Around .........................
Figure 15. Burst with RDY Set One Cycle Before Data .................
Figure 16. Handshake Burst Mode Read
Starting at an Even Address ..........................................................
Figure 17. Handshake Burst Mode Read
Starting at an Odd Address............................................................
41
42
43
43
44
45
46
Flash Command Definitions . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Set Burst Mode Configuration Register Command Sequence 23
Figure 1. Synchronous/Asynchronous State Diagram .................... 23
Table 4. Programmable Wait State Settings ...................................24
Table 5. Initial Access Codes ..........................................................24
Table 6. Wait States for Non-Handshaking .....................................24
Table 7. Burst Read Mode Settings ................................................25
Asynchronous Read ............................................................... 47
Figure 18. Asynchronous Mode Read with Latched Addresses .... 47
Figure 19. Asynchronous Mode Read............................................ 48
Figure 20. Reset Timings ............................................................... 49
Erase/Program Operations ..................................................... 50
Figure 21. Asynchronous Program Operation Timings ..................
Figure 22. Alternate Asynchronous Program Operation Timings...
Figure 23. Synchronous Program Operation Timings....................
Figure 24. Alternate Synchronous Program Operation Timings ....
Figure 25. Chip/Sector Erase Command Sequence ......................
Figure 26. Accelerated Unlock Bypass Programming Timing........
Figure 27. Data# Polling Timings (During Embedded Algorithm) ..
Figure 28. Toggle Bit Timings (During Embedded Algorithm)........
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings
Figure 30. Latency with Boundary Crossing ..................................
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank ...............................................................
Figure 32. Example of Wait States Insertion
(Non-Handshaking Device) ............................................................
Figure 33. Back-to-Back Read/Write Cycle Timings ......................
51
52
53
54
55
56
57
57
58
59
60
61
62
Configuration Register ............................................................ 26
Table 4. Burst Mode Configuration Register ...................................26
Sector Lock/Unlock Command Sequence .............................. 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Program Command Sequence ............................................... 27
Figure 2. Erase Operation............................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 3. Program Operation .......................................................... 29
Command Definitions ............................................................. 30
Table 5. Command Definitions .......................................................30
Flash Write Operation Status . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 4. Data# Polling Algorithm ................................................... 31
SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 63
Read Cycle ............................................................................. 63
Figure 34. SRAM Read Cycle—Address Controlled...................... 63
Figure 35. SRAM Read Cycle ........................................................ 64
RDY: Ready ............................................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 5. Toggle Bit Algorithm......................................................... 32
Write Cycle ............................................................................. 65
Figure 36. SRAM Write Cycle—WE# Control ................................ 65
Figure 37. SRAM Write Cycle—CE1#s Control ............................. 66
Figure 38. SRAM Write Cycle—UB#s and LB#s Control ............... 67
DQ2: Toggle Bit II ................................................................... 32
Table 1. DQ6 and DQ2 Indications .................................................33
Flash Erase And Programming Performance
. 68
3
Am54BDS128AG
July 23, 2002
A D V A N C E
I N F O R M A T I O N
Figure 40. CE2s Controlled Data Retention Mode......................... 69
Flash Latchup Characteristics . . . . . . . . . . . . . . 68
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 68
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 68
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 69
Figure 39. CE1#s Controlled Data Retention Mode........................ 69
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 70
FMA093—93-Ball Fine-Pitch Grid Array 10x 10mm ............... 70
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 71
Revision A (June 19, 2002) .................................................... 71
July 23, 2002
Am54BDS128AG
4
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Am54BDS128AG
Flash Synchronous/Burst
Flash Asynchronous
Speed/V
IO
/
78, 79
88, 89
Speed/V
IO
/
Handshaking Option
(54 MHz) (40 MHz) Handshaking Option 78, 79
Max Initial Access Time,
Max Access Time,
87.5
95
70
ns (t
IACC
)
ns (t
ACC
)
Max Burst Access Time,
Max CE# Access,
13.5
20
70
ns (t
BACC
)
ns (t
CE
)
Max OE# Access,
13.5
20
Max OE# Access, ns (t
OE
)
20
ns (t
OE
)
SRAM
88, 89
85
85
20.5
78, 79
70
70
35
88, 89
85
85
40
Part
Number
V
CC
=
1.65 –
1.95 V
5
Am54BDS128AG
July 23, 2002
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