CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
4.
JA
measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Conditions
PARAMETER
Supply Voltage
Operating Ambient Temperature
Bit Rate
SYMBOL
V
DD
T
A
NRZ data applied to any channel
CONDITION
MIN
1.1
0
1
TYP
1.2
25
MAX
1.3
85
11.1
UNITS
V
°C
Gb/s
Control Pin Characteristics
PARAMETER
Output LOW Logic Level
Output HIGH Logic Level
Input Current
V
DD
= 1.2V, T
A
= +25°C, and V
IN
= 600mV
P-P
, unless otherwise noted.
CONDITION
LOSB
LOSB
Current draw on boost control pin, i.e., CP[A,B]
MIN
MAX
(Note 14) TYP (Note 14) UNITS
0
1000
30
0
250
V
DD
100
mV
mV
µA
SYMBOL
V
OL
V
OH
Electrical Specifications
PARAMETERS
Supply Current
Cable Input Amplitude Range
V
DD
= 1.2V, T
A
= +25°C, and V
IN
= 600mV
P-P
, unless otherwise noted.
CONDITION
Measured differentially at data source before
encountering channel loss; Up to 10m 28AWG
standard twin-axial cable (approx. -27dB @ 5GHz)
Measured on input channel IN[P,N]
Measured on input channel IN[P] or IN[N], with
respect to V
DD
.
MIN
(Note 14)
600
TYP
92
1600
MAX
(Note 14) UNITS
mA
mV
P-P
6
NOTES
SYMBOL
I
DD
V
IN
DC Differential Input Resistance
DC Single-Ended Input Resistance
Input Return Loss Limit
(Differential)
Output Amplitude Range
Differential Output Impedance
Output Return Loss Limit
(Differential)
Output Return Loss Limit (Common
Mode)
S
DD
22
S
CC
22
S
DD
11
V
OUT
80
40
100
50
Note 7
Note 8
120
60
dB
dB
7
8
100MHz to 4.1GHz
4.1GHz to 11.1GHz
Measured differentially at OUT[P] and OUT[N]
with 50 load on both output pins
Measured on OUT[P,N]
100MHz to 4.1GHz
4.1GHz to 11.1GHz
100MHz to 2.5GHz
2.5GHz to 11.1GHz
450
80
650
105
Note 7
Note 8
Note 9
-3
850
120
mV
P-P
dB
dB
dB
dB
7
8
9
10
FN6974 Rev 2.00
Jul 12, 2012
Page 3 of 9
ISL36111
Electrical Specifications
PARAMETERS
Output Residual Jitter
Output Transition Time
Propagation Delay
NOTES:
V
DD
= 1.2V, T
A
= +25°C, and V
IN
= 600mV
P-P
, unless otherwise noted. (Continued)
CONDITION
10.3125Gbps; Up to 10m 28AWG standard twin-
axial cable (approx. -27dB @ 5GHz)
t
r
, t
f
20% to 80%
From IN to OUT
MIN
(Note 14)
TYP
0.35
32
500
MAX
(Note 14) UNITS
UI
ps
ps
NOTES
6, 11, 12
13
SYMBOL
6. The input pins IN[P,N] are DC biased to V
DD
. The specified cable input amplitude range is established by characterization and not production tested,
and is valid so long as the voltages at the input pins IN[P,N] do not violate the voltage ranges specified in “Absolute Maximum Ratings” on page 3.
7. Maximum Reflection Coefficient given by equation SDDXX(dB) = -12 + 2*(f), with f in GHz. Established by characterization and not production tested.
8. Maximum Reflection Coefficient given by equation SDDXX(dB) = -6.3 + 13Log10(f/5.5), with f in GHz. Established by characterization and not
production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not production tested.
10. Limits established by characterization and are not production tested.
11. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured
at the input to the channel). Total jitter (T
J
) is DJ
pp
+ 14.1 x RJ
RMS
12. Measured using a PRBS 2
15
-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only.
13. Rise and fall times measured using a 2GHz clock with a 20ps edge rate.
14. Compliance to limits is assured by characterization and design.
Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 2. The signal from the pattern generator is launched into the twin-ax
cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable through another adapter card. The
ISL36111 output signal is then visualized on a scope to determine signal integrity parameters such as jitter.
Pattern
Generator
SMA
Adapter
Card
100O Twin-Axial
Cable
SMA
Adapter
Card
ISL36111 Eval
Board
Oscilloscope
FIGURE 2. DEVICE CHARACTERIZATION SET UP
FIGURE 3. ISL36111 10.3125Gb/s OUTPUT FOR A 10M 28AWG CABLE
FN6974 Rev 2.00
Jul 12, 2012
Page 4 of 9
ISL36111
CPA
CPB
Limiting
Amplifier
IN[P]
IN[N]
Signal
Detector
Adjustable
Equalizer
Output
Driver
OUT[P]
OUT[N]
DT
LOSB
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM OF THE ISL36111
Operation
The ISL36111 is an advanced lane-extender for high-speed
interconnects. A functional diagram of ISL36111 is shown in
Figure 4. In addition to a robust equalization filter to compensate
for channel loss and restore signal fidelity, the ISL36111
contains unique integrated features to preserve special signaling
protocols typically broken by other equalizers. The signal detect
function is used to mute the channel output when the input
signal falls below the level determined by the Detection
Threshold (DT) pin voltage. This function is intended to preserve
periods of line silence (“DC idle”). Furthermore, the output of the
Signal Detect/DT comparator is used as a loss of signal (LOSB)
indicator to indicate the absence of a received signal.
As illustrated in Figure 4, the core of the high-speed signal path
in the ISL36111 is a sophisticated equalizer followed by a
limiting amplifier. The equalizer compensates for skin loss,
dielectric loss, and impedance discontinuities in the
transmission channel. The equalizer is followed by a limiting
amplification stage that provides a clean output signal with full
amplitude swing and fast rise-fall times for reliable signal
decoding in a subsequent receiver.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CP-PIN
CONNECTIVITY
CPA
Float
Float
GND
Float
VDD
GND
GND
VDD
VDD
CPB
Float
GND
VDD
VDD
Float
Float
GND
GND
VDD
BOOST LEVEL
0
1
2
3
4
5
6
7
8
CML Input and Output Buffers
The input and output buffers for the high-speed data channel in
the ISL36111 are implemented using CML. Equivalent input and
output circuits are shown in Figures 5 and 6.
V
DD
IN[P]
Adjustable Equalization Boost
ISL36111 features a settable equalizer for custom signal
restoration. The flexibility of this adjustable compensation
architecture enables signal fidelity to be optimized based on a
given application, providing support for a wide variety of channel
characteristics and data rates ranging from 2.5Gb/s to
11.1Gb/s. Because the boost level is externally set rather than
internally adapted, the ISL36111 provides reliable
communication from the very first bit transmitted. There is no
time needed for adaptation and control loop convergence.
Furthermore, there are no pathological data patterns that will
cause the ISL36111 to move to an incorrect boost level.
50O
1
st
Filter
Stage
Control Pin Boost Setting
The connectivity of the CP pins are used to determine the boost
level of ISL36111. Table 1 defines the mapping from the 2-bit CP
word to the 9 available boost levels.
50O
IN[N]
FIGURE 5. CML INPUT EQUIVALENT CIRCUIT FOR THE ISL36111
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