DATASHEET
ISL62881, ISL62881B
Single-Phase PWM Regulator for IMVP-6.5™ Mobile CPUs and GPUs
The ISL62881 is a single-phase PWM buck regulator for
miroprocessor or graphics processor core power supply. It uses an
integrated gate driver to provide a complete solution. The PWM
modulator of ISL62881 is based on Intersil's Robust Ripple
Regulator (R
3
) technology™. Compared with traditional
modulators, the R
3
™ modulator commands variable switching
frequency during load transients, achieving faster transient
response. With the same modulator, the switching frequency is
reduced at light load, increasing the regulator efficiency.
The ISL62881 can be configured as CPU or graphics Vcore
controller and is fully compliant with IMVP-6.5™ specifications. It
responds to DPRSLPVR signals by entering/exiting diode
emulation mode. It reports the regulator output current through
the IMON pin. It senses the current by using either discrete
resistor or inductor DCR whose variation over-temperature can
be thermally compensated by a single NTC thermistor. It uses
differential remote voltage sensing to accurately regulate the
processor die voltage. The adaptive body diode conduction
time reduction function minimizes the body diode conduction
loss in diode emulation mode. User-selectable overshoot
reduction function offers an option to aggressively reduce the
output capacitors as well as the option to disable it for users
concerned about increased system thermal stress.
Maintaining all the ISL62881 functions, the ISL62881B offers
VR_TT# function for thermal throttling control. It also offers the
split LGATE function to further improve light load efficiency.
FN6924
Rev 3.00
June 16, 2011
Features
• Precision Core Voltage Regulation
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Voltage Identification Input
- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Supports Multiple Current Sensing Methods
- Lossless Inductor DCR Current Sensing
- Precision Resistor Current Sensing
• Superior Noise Immunity and Transient Response
• Current Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Integrated Gate Driver
• Split LGATE Driver to Increase Light-Load Efficiency (for
ISL62881B)
• Adaptive Body Diode Conduction Time Reduction
• User-selectable Overshoot Reduction Function
• Capable of Disabling the Droop Function
• Audio-filtering for GPU Application
• Small Footprint 28 Ld 4x4 TQFN Package
• Pb-Free (RoHS Compliant)
Applications
• Notebook Computers
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL62881HRTZ
ISL62881BHRTZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL62881, ISL62881B.
For more information on MSL please see techbrief
TB363.
PART
MARKING
628 81HRTZ
62881B HRTZ
TEMP. RANGE
(°C)
-10 to +100
-10 to +100
PACKAGE
(Pb-Free)
28 Ld 4x4 TQFN
32 Ld 5x5 TQFN
PKG.
DWG. #
L28.4x4
L32.5x5E
FN6924 Rev 3.00
June 16, 2011
Page 1 of 35
ISL62881, ISL62881B
Pin Configurations
ISL62881
(28 LD TQFN)
TOP VIEW
DPRSLPVR
DPRSLPVR
CLK_EN#
VR_ON
ISL62881B
(32 LD TQFN)
TOP VIEW
VR_ON
VID4
VID6
VID5
VID3
28
CLK_EN# 1
PGOOD 2
RBIAS
VW
3
4
27
26 25
24
23
22
21 VID1
20 VID0
19 VCCP
PGOOD 1
RBIAS 2
VR_TT# 3
NTC 4
GND 5
VW 6
COMP 7
FB 8
32 31 30 29 28 27 26 25
24 VID1
23 VID0
22 VCCP
GND PAD
(BOTTOM)
21 LGATEb
20 LGATEa
19 VSSP
18 PHASE
17 UGATE
9 10 11 12 13 14 15 16
VIN
ISUM-
ISUM+
IMON
BOOT
VSEN
RTN
VDD
COMP 5
FB
VSEN
6
7
8
RTN
9
ISUM-
GND PAD
(BOTTOM)
18 LGATE
17 VSSP
16 PHASE
15 UGATE
10
ISUM+
11
VDD
12
VIN
13
IMON
14
BOOT
Pin Function Descriptions
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals are
referenced to the GND pin.
COMP
This pin is the output of the error amplifier. Also, a resistor across this
pin and GND adjusts the overcurrent threshold.
CLK_EN#
Open drain output to enable system PLL clock; goes active 13
switching cycles after V
core
is within 10% of V
boot
.
FB
This pin is the inverting input of the error amplifier.
VSEN
Remote core voltage sense input. Connect to microprocessor die.
PGOOD
Power-Good open-drain output indicating when the regulator is
able to supply regulated voltage. Pull-up externally with a 680
resistor to VCCP or 1.9k to 3.3V.
RTN
Remote voltage sensing return. Connect to ground at
microprocessor die.
RBIAS
A resistor to GND sets internal current reference. A 147k
resistor sets the controller for CPU core application and a 47k
resistor sets the controller for GPU core application.
ISUM- and ISUM+
Droop current sense input.
VDD
5V bias power.
VR_TT#
Thermal overload output indicator.
VIN
Battery supply voltage, used for feed-forward.
NTC
Thermistor input to VR_TT# circuit.
IMON
An analog output. IMON outputs a current proportional to the
regulator output current.
VW
A resistor from this pin to COMP programs the switching
frequency (8k gives approximately 300kHz).
BOOT
Connect an MLCC capacitor across the BOOT and the PHASE
pins. The boot capacitor is charged through an internal boot
FN6924 Rev 3.00
June 16, 2011
Page 2 of 35
VID2
VID6
VID5
VID4
VID2
VID3
ISL62881, ISL62881B
diode connected from the VCCP pin to the BOOT pin, each time
the PHASE pin drops below VCCP minus the voltage dropped
across the internal boot diode.
LGATEb (For ISL62881B)
Another output of the low-side MOSFET gate driver. This gate
driver will be pulled low when the DPRSLPVR pin logic is high.
Connect the LGATEb pin to the gate of the low-side MOSFET that
is idle in deeper sleep mode.
UGATE
Output of the high-side MOSFET gate driver. Connect the UGATE
pin to the gate of the high-side MOSFET.
VCCP
Input voltage bias for the internal gate drivers. Connect +5V to
the VCCP pin. Decouple with at least 1µF of an MLCC capacitor to
VSSP1 and VSSP2 pins respectively.
PHASE
Current return path for the high-side MOSFET gate driver. Connect
the PHASE pin to the node consisting of the high-side MOSFET
source, the low-side MOSFET drain and the output inductor.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB and VID6 = MSB.
VSSP
Current return path for the low-side MOSFET gate driver. Connect
the VSSP pin to the source of the low-side MOSFET through a low
impedance path, preferably in parallel with the trace connecting
the LGATE pin to the gate of the low-side MOSFET.
VR_ON
Voltage regulator enable input. A high level logic signal on this
pin enables the regulator.
LGATE (for ISL62881)
Output of the low-side MOSFET gate driver. Connect the LGATE
pin to the gate of the low-side MOSFET.
DPRSLPVR
A high level logic signal on this pin puts the ISL62881 in 1-phase
diode emulation mode. If R
BIAS
= 47k (GPU VR application), this
pin also controls V
core
slew rate. V
core
slews at 5mV/µs for
DPRSLPVR = 0 and 10mV/µs for DPRSLPVR = 1. If R
BIAS
= 147k
(CPU VR application), this pin doesn’t control V
core
slew rate.
LGATEa (for ISL62881B)
Output of the low-side MOSFET gate driver that is always active.
Connect the LGATEa pin to the gate of the low-side MOSFET that
is active all the time.
FN6924 Rev 3.00
June 16, 2011
Page 3 of 35
ISL62881, ISL62881B
Block Diagram
VIN VSEN
PGOOD
CLK_EN#
VDD
VR_ON
MODE
CONTROL
DPRSLPVR
RBIAS
PROTECTION
VID0
VID1
VID2
VID3
VID4
VID5
VID6
RTN
FB
COMP
VW
Imon
IMON
ISUM+
ISUM-
CURRENT
SENSE
2.5X
VIN
VDAC
VIN
DAC
AND
SOFT
START
WOC OC
CLOCK
VDAC
COMP
VW
FLT
PGOOD AND
CLK_EN#
LOGIC
6µA 54µA
1.20V
1.24V
VR_TT#
NTC
ISL62881B
ONLY
BOOT
PWM CONTROL LOGIC
DRIVER
UGATE
PHASE
E/A
SHOOT
THROUGH
PROTECTION
DRIVER
VCCP
LGATEA
VSSP
ISL62881 ONLY
Idroop
WOC
MODULATOR
COMP
60µA
CURRENT
COMPARATORS
OC
DRIVER
LGATEB
ISL62881B
ONLY
GND
ADJ. OCP
THRESHOLD
COMP
FN6924 Rev 3.00
June 16, 2011
Page 4 of 35
ISL62881, ISL62881B
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE). . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD + 0.3V
. . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . . . . . . . . . . . . -0.3V to +7V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5)
JA
(°C/W)
JC
(°C/W)
28 Ld TQFN Package . . . . . . . . . . . . . . . . . .
40
3
32 Ld TQFN Package . . . . . . . . . . . . . . . . . .
32
3
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
limits apply over the operating temperature range, -10°C to +100°C.
SYMBOL
Operating Conditions: V
DD
= 5V, T
A
= -10°C to +100°C, f
SW
= 300kHz, unless otherwise noted.
Boldface
MIN
(Note 6)
MAX
(Note 6) UNITS
TEST CONDITIONS
TYP
INPUT POWER SUPPLY
+5V Supply Current
I
VDD
I
VIN
R
VIN
POR
r
POR
f
VR_ON = 1V
VR_ON = 0V
Battery Supply Current
V
IN
Input Resistance
Power-On-Reset Threshold
VR_ON = 0V
VR_ON = 1V
V
DD
rising
V
DD
falling
No load; closed loop, active mode range
VID = 0.75V to 1.50V
VID = 0.5V to 0.7375V
VID = 0.3V to 0.4875V
V
BOOT
Maximum Output Voltage
Minimum Output Voltage
R
BIAS
Voltage
V
CC_CORE(max)
V
CC_CORE(min)
VID = [0000000]
VID = [1111111]
R
BIAS
= 147k
f
SW(nom)
RF
SET
= 7k, V
COMP
= 1V
1.45
4.00
900
4.35
4.15
4.5
3.2
4.0
1
1
mA
µA
µA
k
V
V
SYSTEM AND REFERENCES
System Accuracy
%Error (V
CC_CORE
)
-0.5
-8
-15
+0.5
+8
+15
%
mV
mV
V
V
V
1.49
V
1.0945 1.100 1.1055
1.500
0
1.47
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
AMPLIFIERS
Current-Sense Amplifier Input
Offset
Error Amp DC Gain
Error Amp Gain-Bandwidth
Product
A
v0
GBW
C
L
= 20pF
I
FB
= 0A
-0.15
90
18
+0.15
mV
dB
MHz
295
200
310
325
500
kHz
kHz
FN6924 Rev 3.00
June 16, 2011
Page 5 of 35
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