®
HI-200, HI-201
Data Sheet
April 6, 2005
FN3121.8
Dual/Quad SPST, CMOS Analog Switches
HI-200/HI-201 (dual/quad) are monolithic devices comprising
independently selectable SPST switches which feature fast
switching speeds (HI-200 240ns, and HI-201 185ns)
combined with low power dissipation (15mW at 25
o
C). Each
switch provides low “ON” resistance operation for input signal
voltage up to the supply rails and for signal current up to
80mA. Rugged DI construction eliminates latch-up and
substrate SCR failure modes.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. HI-200/HI-201 are ideal components for use in
high frequency analog switching. Typical applications
include signal path switching, sample and hold circuit, digital
filters, and operational amplifier gain switching networks.
Features
•
Pb-Free Available (RoHS Compliant)
• Analog Voltage Range . . . . . . . . . . . . . . . . . . . . . . .
±15V
• Analog Current Range . . . . . . . . . . . . . . . . . . . . . . . 80mA
• Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240ns
• Low r
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Ω
• Low Power Dissipation. . . . . . . . . . . . . . . . . . . . . . .15mW
• TTL/CMOS Compatible
Applications
• High Frequency Analog Switching
• Sample and Hold Circuits
• Digital Filters
Ordering Information
PART NUMBER
HI3-0200-5Z
(Note)
HI1-0201-2
HI1-0201-4
HI1-0201-5
HI3-0201-5
HI3-0201-5Z
(Note)
HI4P0201-5
HI4P0201-5Z
(Note)
HI9P0201-5
HI9P0201-5Z
(Note)
HI9P0201-9
HI9P0201-9Z
(Note)
TEMP.
RANGE (°C)
0 to 75
-55 to 125
-25 to 85
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
0 to 75
-40 to 85
-40 to 85
PACKAGE
14 Ld PDIP*
(Pb-free)
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld PDIP*
(Pb-free)
20 Ld PLCC
20 Ld PLCC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
PKG.
DWG. #
E14.3
F16.3
F16.3
F16.3
E16.3
E16.3
N20.35
N20.35
M16.15
M16.15
M16.15
M16.15
• Operational Amplifier Gain Switching Networks
Functional Diagram
V+
V
REF
INPUT
SOURCE
LOGIC
INPUT
GATE
REFERENCE,
LEVEL SHIFTER,
AND DRIVER
SWITCH
CELL
GATE
DRAIN
OUTPUT
V-
TRUTH TABLE
LOGIC
0
1
HI-200
ON
OFF
HI-201
ON
OFF
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE:
Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate ter-
mination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or ex-
ceed the Pb-free requirements of IPC/JEDEC J STD-020. Pb-free
PDIPs can be used for through hole wave solder processing only. They
are not intended for use in Reflow solder processing applications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2001, 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-200, HI-201
Pinouts
(Switches Shown For Logic “1” Input)
HI-201 (CERDIP, PDIP, SOIC)
TOP VIEW
OUT1
14 A
1
13 NC
12 V+
11 NC
10 IN1
9 OUT1
8 V
REF
A
1
OUT1
IN1
1
2
3
16 A
2
15 OUT2
14 IN2
13 V+
12 V
REF
11 IN3
10 OUT3
9 A
3
IN1
V-
NC
GND
IN4
4
5
6
7
8
9
OUT4
10
A4
11
NC
12
A3
13
OUT3
HI-200 (PDIP)
TOP VIEW
A
2
1
NC 2
GND 3
NC 4
IN2 5
OUT2 6
V- 7
HI-201 (PLCC)
TOP VIEW
OUT2
19
18 IN2
17 V+
16 NC
15 V
REF
14 IN3
NC
1
A1
3
2
20
V- 4
GND
IN4
OUT4
A
4
5
6
7
8
Schematic Diagrams
TTL/CMOS REFERENCE CIRCUIT V
REF
CELL
HI-200
V+
R
6
300
Q
P2
Q
P1
Q
P4
Q
N1
D
3
R
3
24.2K
Q
N2
R
4
5.4K
R
5
7.9K
M
N15
V-
GND
GND
M
N16
M
N17
R
7
100K
M
N14
D
3
Q
P3
Q
N4
M
P13
Q
P5
TO P
2
V
REF
V+
R
6
600
Q
P2
Q
P1
Q
P4
Q
N1
R
3
24.2K
Q
N2
R
4
5.4K
R
5
7.9K
M
N15
V-
M
N16
M
N17
M
N14
M
P14
Q
N3
Q
P6
R
7
100K
V
LL
Q
P3
Q
N4
M
P13
Q
P5
TO P
2
V
REF
TTL/CMOS REFERENCE CIRCUIT V
REF
CELL
HI-201
R
2
5K
R
2
5K
V
LL
GND
GND
2
A2
FN3121.8
April 6, 2005
HI-200, HI-201
Schematic Diagrams
(Continued)
SWITCH CELL
A’
Q
N11
V+
Q
N12
INPUT
Q
P11
Q
N13
OUTPUT
V-
Q
P12
A’
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
V+
Q
P3
Q
P1
Q
P5
Q
P4
A’
V+
Q
N1
Q
P7
D
1
TO V
LL
TO V
REF
200Ω
D
2
Q
P2
A
V-
Q
P6
Q
P8
Q
P9
Q
P10
Q
N8
Q
N6
Q
N7
Q
N9
Q
N10
A’
Q
N2
Q
N4
Q
N5
Q
N3
V-
3
FN3121.8
April 6, 2005
HI-200, HI-201
Absolute Maximum Ratings
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . 44V (±22)
V
REF
to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V, -5V
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Input Voltage (One Switch) . . . . . . . . . . (V+) +2V to (V-) -2V
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . . .
75
20
PLCC Package. . . . . . . . . . . . . . . . . . .
80
N/A
PDIP Package* . . . . . . . . . . . . . . . . . .
95
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
110
N/A
Maximum Storage Temperature . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Maximum Junction Temperature (Hermetic Packages). . . . . 175
o
C
Maximum Junction Temperature (Plastic Packages) . . . . . . 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . 300
o
C
(PLCC and SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in reflow solder processing
applications.
Operating Conditions
Temperature Ranges
HI-201-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
HI-201-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to 85
o
C
HI-200-5, HI-201-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 75
o
C
HI-201-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; V
REF
= Open; V
AH
(Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V
TEST
CONDITIONS
TEMP
(
o
C)
-2
MIN
TYP
MAX
MIN
-4, -5, -9
TYP
MAX
UNITS
PARAMETER
DYNAMIC CHARACTERISTICS
Switch ON Time, t
ON
HI-200
HI-201
25
25
Full
-
-
-
240
185
1000
500
500
-
-
-
-
240
185
1000
-
-
-
ns
ns
ns
Switch OFF Time, t
OFF
HI-200
HI-201
25
25
Full
Off Isolation
HI-200
HI-201
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
D(OFF)
Output Switch Capacitance, C
D(ON)
Digital Input Capacitance, C
A
Drain-to-Source Capacitance, C
DS(OFF)
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
AL
Input High Threshold, V
AH
Input Leakage Current (High or Low), I
A
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
S
ON Resistance, r
ON
(Note 2)
Full
25
Full
-15
-
-
-
55
80
+15
70
100
-15
-
-
-
55
72
+15
80
100
V
Ω
Ω
(Note 3)
Full
Full
Full
-
2.4
-
-
-
-
0.8
-
1.0
-
2.4
-
-
-
-
0.8
-
1.0
V
V
µA
(Note 4)
25
25
25
25
25
25
25
-
-
-
-
-
-
-
70
80
5.5
5.5
11
5
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
70
80
5.5
5.5
11
5
0.5
-
-
-
-
-
-
-
dB
dB
pF
pF
pF
pF
pF
-
-
-
330
220
1000
500
500
-
-
-
-
500
220
1000
-
-
-
ns
ns
ns
4
FN3121.8
April 6, 2005
HI-200, HI-201
Electrical Specifications
PARAMETER
OFF Input Leakage Current, I
S(OFF)
HI-200
HI-201
Supplies = +15V, -15V; V
REF
= Open; V
AH
(Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V
(Continued)
TEST
CONDITIONS
(Note 6)
TEMP
(
o
C)
25
Full
25
Full
OFF Output Leakage Current, I
D(OFF)
HI-200
HI-201
(Note 6)
25
Full
25
Full
ON Leakage Current, I
D(ON)
HI-200
HI-201
(Note 6)
25
Full
25
Full
POWER SUPPLY CHARACTERISTICS
(Note 5)
Power Dissipation, P
D
25
Full
Current, I+
25
Full
Current, I-
25
Full
NOTES:
2. V
OUT
=
±10V,
I
OUT
= 1mA.
3. Digital Inputs are MOS gates: typical leakage is < 1nA.
4. V
A
= 5V, R
L
= 1kΩ, C
L
= 10pF, V
S
= 3V
RMS
, f = 100kHz.
5. V
A
= +3V or V
A
= 0V for Both Switches.
6. Refer to Leakage Current Measurements (Figure 2).
-
-
-
-
-
-
15
-
0.5
-
0.5
-
-
60
-
2.0
-
2.0
-
-
-
-
-
-
15
-
0.5
-
0.5
-
-
60
-
2.0
-
2.0
mW
mW
mA
mA
mA
mA
-2
MIN
-
-
-
-
-
-
-
-
-
-
-
-
TYP
1
100
2
-
1
100
2
35
1
100
2
-
MAX
5
500
5
500
5
500
5
500
5
500
5
500
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-4, -5, -9
TYP
1
10
2
-
1
10
2
35
1
10
2
-
MAX
50
500
50
250
50
500
50
250
50
500
50
250
UNITS
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
nA
Test Circuits and Waveforms
T
A
= 25
o
C, V
SUPPLY
= ±±15V, V
AH
= 2.4V, V
AL
= 0.8V and V
REF
= Open
1mA
2
-
r
ON
= ------------
1mA
IN
±V
IN
V
V
2
OUT
FIGURE 1A. ON RESISTANCE TEST CIRCUIT
5
FN3121.8
April 6, 2005
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