DATASHEET
MULTIPLIER AND ZERO DELAY BUFFER
Description
The ICS570 is a high-performance Zero Delay Buffer (ZDB)
which integrates IDT’s proprietary analog/digital Phase
Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of IDT’s ClockBlocks
TM
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage requirements.
The zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both output
clocks, giving the appearance of no delay through the
device. There are two outputs on the chip, one being a
low-skew divide by two of the other output. The device
incorporates an all-chip power down/tri-state mode that
stops the internal PLL and puts both outputs into a high
impedance state.
The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay through
other devices.
The ICS570 A and B versions were designed to improve
input to output jitter from the original ICS570M version, and
are recommended for all new designs.
ICS570
Features
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8-pin SOIC package
Available in Pb (lead) free package
Pin-for-pin replacement and upgrade to ICS570M
Functional equivalent to AV9170 (not a pin-for-pin
replacement)
Low input to output skew of 300 ps max (>60 MHz
outputs)
Ability to choose between 14 different multipliers from
0.5x to 32x
Output clock frequency up to 170 MHz at 3.3 V
Can recover degraded input clock duty cycle
Output clock duty cycle of 45/55
Power Down and Tri-State Mode
Passes spread spectrum clock modulation
Full CMOS clock swings with 25 mA drive capability at
TTL levels
Advanced, low power CMOS process
ICS570B has an operating voltage of 3.3 V (±5%)
ICS570A has an operating voltage of 5.0 V (±5%)
Industrial temperature version available
Block Diagram
IC L K
S 1 :0
F B IN
d ivid e
by N
Phase
D e te c to r,
C h a rg e
Pum p,
and Loop
F ilte r
VCO
/2
C LK
C LK2
E xte rn a l fe e d b a ck ca n co m e fro m C L K o r C L K /2 (se e ta b le o n p a g e 2 )
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER
1
ICS570
REV K 073007
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Assignment
S1
VDD
GND
ICLK
1
2
3
4
8
7
6
5
CLK/2
CLK
S0
FBIN
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
FBIN from
CLK
CLK
#1
0
0
0
M
M
M
1
1
1
#6
0
M
1
0
M
1
0
M
1
S1 S0
FBIN from
CLK/2
CLK
ICS570B (3.3 V)
ICS570A (5.0 V)
CLK/2
CLK/2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
pin #7 pin #8 pin #7 pin #8
Power Down and Tri-State
x3
x1.5
x6
x3
x4
x2
x8
x4
x8
x4
x16
x8
x6
x3
x12
x6
x10
x5
x20
x10
x1
/2
x2
x1
x16
x8
x32
x16
x2
x1
x4
x2
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
-
3.75 to 28
2.75 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
11 to 85
1.5 to 5
5.5 to 37.5
-
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
1.5 to 5
2.5 to 37.5
*Input range with CLK feedback is double that for CLK/2
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER
2
ICS570
REV K 073007
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
S1
VDD
GND
ICLK
FBIN
S0
CLK
CLK/2
Pin
Type
Input
Power
Power
Input
Input
Input
Output
Output
Pin Description
Select 1 for output clock. Connect to GND, VDD, or float per decoding
Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding
Clock output per table above.
Clock output per table above. Low skew divide by two of pin 7 clock.
External Components
The ICS570 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be connected
close to the part to minimize lead inductance. No external power supply filtering is required for this device. A 33Ω
series terminating resistor can be used next to each output pin.
Recommended Circuit
S1
VDD
GND
S0
Input
FBIN
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
CLK
CLK
CLK/2
ICLK
ICLK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER
3
ICS570
REV K 073007
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the
CLK/2 could be a falling edge compared with ICLK. IDT recommends using CLK/2 feedback whenever possible.
This will synchronize the rising edges of all three clocks.
Clock Period Jitter Tables (ICS570A)
All jitter values are considered typical measured at 25° C with 27Ω termination resistor and 15 pF loads on both CLK
and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to
improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
M
1
1
1
S
M
1
0
M
1
0
M
1
CLKIN
8.333
6.25
3.125
4.167
2.5
25
1.5625
12.5
Multiplier
6x
8x
16x
12x
20x
2x
32x
4x
CLK = 50M
P to P
±115
±115
±120
±120
±120
±120
±120
±120
1 sigma
80
80
80
90
80
70
80
80
CLK/2 = 25M
Multiplier
P to P
3x
4x
8x
6x
10x
1x
16x
2x
±65
±60
±55
±60
±60
±55
±50
±55
1 sigma
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
M
1
1
1
S
M
1
0
M
1
0
M
1
CLKIN
16.667
12.5
6.25
8.333
5
50
3.125
25
CLK = 100M
Multiplier
P to P
6x
8x
16x
12x
20x
2x
32x
4x
±135
±140
±140
±140
±135
±120
±135
±130
1 sigma
100
100
110
110
100
90
100
90
CLK/2 = 50M
Multiplier
P to P
3x
4x
8x
6x
10x
1x
16x
2x
±55
±50
±55
±55
±50
±50
±55
±65
1 sigma
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
M
S
M
1
0
M
1
CLKIN
25
18.375
9.375
12.5
7.5
CLK = 150M
Multiplier
P to P
6x
8x
16x
12x
20x
±160
±165
±170
±160
±160
1 sigma
120
120
120
120
120
CLK/2 = 75M
Multiplier
P to P
3x
4x
8x
6x
10x
±55
±55
±50
±55
±55
1 sigma
20
20
20
20
20
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER
4
ICS570
REV K 073007
ICS570
MULTIPLIER AND ZERO DELAY BUFFER
ZDB AND MULTIPLIER
1
1
1
0
M
1
75
4.6875
37.5
2x
32x
4x
±155
±165
±160
110
120
110
1x
16x
2x
±55
±55
±50
20
20
20
Clock Period Jitter Tables (ICS570B)
All jitter values are considered typical measured at 25° C with 27Ω termination resistor and 15 pF loads on both CLK
and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left unconnected to
improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
M
1
1
1
S
M
1
0
M
1
0
M
1
CLKIN
8.333
6.25
3.125
4.167
2.5
25
1.5625
12.5
Multiplier
6x
8x
16x
12x
20x
2x
32x
4x
CLK = 50M
P to P
±110
±125
±130
±120
±115
±130
±120
±120
1 sigma
80
90
90
90
90
50
90
60
CLK/2 = 25M
Multiplier
P to P
3x
4x
8x
6x
10x
1x
16x
2x
±55
±50
±55
±55
±55
±55
±55
±55
1 sigma
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
M
1
1
1
S
M
1
0
M
1
0
M
1
CLKIN
16.667
12.5
6.25
8.333
5
50
3.125
25
CLK = 100M
Multiplier
P to P
6x
8x
16x
12x
20x
2x
32x
4x
±100
±100
±110
±100
±105
±90
±95
±105
1 sigma
70
70
80
70
70
60
70
70
CLK/2 = 50M
Multiplier
P to P
3x
4x
8x
6x
10x
1x
16x
2x
±45
±45
±45
±45
±40
±40
±45
±60
1 sigma
20
20
20
20
20
20
20
20
Absolute and One Sigma Jitter (ps)
S
0
0
M
M
S
M
1
0
M
CLKIN
25
18.375
9.375
12.5
CLK = 150M
Multiplier
P to P
6x
8x
16x
12x
±115
±120
±130
±130
1 sigma
70
80
90
90
CLK/2 = 75M
Multiplier
P to P
3x
4x
8x
6x
±50
±50
±50
±45
1 sigma
20
20
20
20
IDT™ / ICS™
MULTIPLIER AND ZERO DELAY BUFFER
5
ICS570
REV K 073007
分立器件
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