Am29F080B
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21503
Revision
G
Amendment
+2
Issue Date
June 14, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29F080B
8 Megabit (1 M x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
5.0 V
±
10%, single power supply operation
— Minimizes system level power requirements
■
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F080 device
■
High performance
— Access times as fast as 55 ns
■
Low power consumption
— 25 mA typical active read current
— 30 mA typical program/erase current
— 1 µA typical standby current (standard access
time to active mode)
■
Flexible sector architecture
— 16 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
— Supports full chip erase
— Group sector protection:
A hardware method of locking sector groups to
prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code
changes in previously locked sectors
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
■
Minimum 1,000,000 program/erase cycles per
sector guaranteed
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package options
— 40-pin TSOP
— 44-pin SO
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase cycle completion
■
Ready/Busy# output (RY/BY#)
— Provides a hardware method for detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
■
Hardware reset pin (RESET#)
— Resets internal state machine to the read mode
■
Command sequence optimized for mass storage
— Specific addresses not required for unlock cycles
3
Publication#
21503
Rev:
G
Amendment/+2
Issue Date:
June 14, 2004
GENERAL DESCRIPTION
The Am29F080B is an 8 Mbit, 5.0 volt-only Flash mem-
ory organized as 1,048,576 bytes. The 8 bits of data
appear on DQ0–DQ7. The Am29F080B is offered in
40-pin TSOP and 44-pin SO packages. This device is
designed to be programmed in-system with the standard
system 5.0 volt V
CC
supply. A 12.0 volt V
PP
is not re-
quired for program or erase operations. The device can
also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F080, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 70, 90,
120, and 150 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus conten-
tion, the device has separate chip enable (CE#), write
enable (WE#), and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
4
Am29F080B
June 14, 2004
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29F080B Device Bus Operations ................................10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23
Figure 6. Maximum Negative Overshoot Waveform ...................... 23
Figure 7. Maximum Negative Overshoot Waveform ...................... 23
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
TTL/NMOS Compatible .......................................................... 24
CMOS Compatible .................................................................. 24
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Test Setup ....................................................................... 25
Table 2. Test Specifications ........................................................... 25
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 1. Am29F080B Sector Address Table ...................................12
Key to Switching Waveforms . . . . . . . . . . . . . . . 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Read-only Operations ............................................................. 26
Figure 9. Read Operation Timings ................................................. 26
Hardware Reset (RESET#) .................................................... 27
Figure 10. RESET# Timings .......................................................... 27
Autoselect Mode ..................................................................... 12
Table 2. Am29F080B Autoselect Codes (High Voltage Method) ....12
Erase and Program Operations .............................................. 28
Figure 11. Program Operation Timings .......................................... 29
Figure 12. Chip/Sector Erase Operation Timings .......................... 30
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 31
Figure 14. Toggle Bit Timings (During Embedded Algorithms) ...... 31
Figure 15. DQ2 vs. DQ6 ................................................................. 32
Sector Group Protection/Unprotection .................................... 13
Table 3. Sector Group Addresses ...................................................13
Temporary Sector Group Unprotect ....................................... 13
Figure 1. Temporary Sector Group Unprotect Operation ................13
Hardware Data Protection ...................................................... 14
Low V
CC
Write Inhibit ......................................................................14
Write Pulse “Glitch” Protection ........................................................14
Logical Inhibit ..................................................................................14
Power-Up Write Inhibit ....................................................................14
Temporary Sector Unprotect .................................................. 32
Figure 16. Temporary Sector Group Unprotect Timing Diagram ... 32
Erase and Program Operations .............................................. 33
Alternate CE# Controlled Writes .................................................... 33
Figure 17. Alternate CE# Controlled Write Operation Timings ...... 34
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 14
Byte Program Command Sequence ....................................... 15
Figure 2. Program Operation ..........................................................15
Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 16
Figure 3. Erase Operation ...............................................................17
Command Definitions ............................................................. 18
Table 4. Am29F080B Command Definitions ..................................18
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
DQ7: Data# Polling ................................................................. 19
Figure 4. Data# Polling Algorithm ...................................................19
RY/BY#: Ready/Busy# ........................................................... 20
DQ6: Toggle Bit I .................................................................... 20
DQ2: Toggle Bit II ................................................................... 20
Reading Toggle Bits DQ6/DQ2 .............................................. 20
DQ5: Exceeded Timing Limits ................................................ 21
DQ3: Sector Erase Timer ....................................................... 21
Figure 5. Toggle Bit Algorithm .........................................................21
Table 5. Write Operation Status ......................................................22
Erase and Programming Performance . . . . . . 35
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 35
TSOP and SO Pin Capacitance . . . . . . . . . . . . . 35
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36
SO 044—44-Pin Small Outline Package ................................ 36
TS 040—40-Pin Standard Thin Small Outline Package ......... 37
TSR040—40-Pin Reverse Thin Small Outline Package ......... 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision A (July 1997) ............................................................ 39
Revision B (January 1998) ..................................................... 39
Revision C (January 1998) ..................................................... 39
Revision D (May 1998) ........................................................... 39
Revision E (January 1999) ..................................................... 39
Revision E+1 (March 23, 1999) .............................................. 39
Revision E+2 (April 9, 1999) ................................................... 39
Revision F (November 15, 1999) ............................................ 39
Revision F+1 (May 18, 2000) ................................................. 39
Revision G (December 4, 2000) ............................................. 39
Revision G+1 (January 3, 2002) ............................................. 40
Revision G+2 (June 11, 2004) ................................................ 40
June 14, 2004
Am29F080B
5
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