FINAL
Am27C040
4 Megabit (512 K x 8-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
s
Fast access time
— Available in speed options as fast as 90 ns
s
Low power consumption
— <10 µA typical CMOS standby current
s
JEDEC-approved pinout
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
— Easy upgrade from 28-pin JEDEC EPROMs
s
Single +5 V power supply
s
±10%
power supply tolerance standard
s
100% Flashrite™ programming
— Typical programming time of 1 minute
s
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
s
High noise immunity
s
Compact 32-pin DIP, PDIP, PLCC packages
GENERAL DESCRIPTION
The Am27C040 is a 4 Mbit ultraviolet erasable pro-
grammable read-only memory. It is organized as 512K
bytes, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The device is available in windowed
ceramic DIP packages and plastic one-time program-
mable (OTP) packages.
Data can be typically accessed in less than 90 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 100 mW in active mode,
and 50 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses) re-
sulting in typical programming time of 1 minute.
BLOCK DIAGRAM
V
CC
V
SS
V
PP
OE#
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
A0–A18
Address
Inputs
Data Outputs
DQ0–DQ7
Output
Buffers
CE#/PGM#
Y
Gating
X
Decoder
4,194,304-Bit
Cell Matrix
14971H-1
Publication#
14971
Rev:
H
Amendment/0
Issue Date:
August 25, 1999
F I N A L
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 30 W seconds/cm
2
is required
to completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm
2
for 30 to 35
minutes. The device should be directly under and about
one inch from the source and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
that particular device. A high-level CE#/PGM# input in-
hibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# at V
IL
, CE#/
PGM# at V
IH
, and V
PP
between 12.5 V and 13.0 V.
Auto Select Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C
±
5°C
ambient temperature range that is required when pro-
gramming the device.
To activate this mode, the programming equipment
must force V
H
on address line A9. Two identifier bytes
may then be sequenced from the device outputs by tog-
gling address line A0 from V
IL
to V
IH
(that is, changing
the address from 00h to 01h). All other address lines
must be held at V
IL
during the autoselect mode.
Byte 0 (A0 = V
IL
) represents the manufacturer code,
and Byte 1 (A0 = V
IH
), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The programming mode is entered when 12.75 V
±
0.25 V is applied to the V
PP
pin, CE#/PGM# is at V
IL
and OE# is at V
IH
.
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data output pins.
The flowchart in the EPROM Products Data Book, Pro-
gramming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces pro-
gramming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reli-
ably program the data. After each pulse is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each ad-
dress of the device. This part of the algorithm is done at
V
CC
= 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at V
CC
= V
PP
= 5.25 V.
Please refer to the EPROM Products Data Book, Sec-
tion 5 for the programming flow chart and characteris-
tics.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the power to the device and is typ-
ically used to select the device. OE# enables the device
to output data, independent of device selection. Ad-
dresses must be stable for at least t
ACC
–t
OE
. Refer to
the Switching Waveforms section for the timing dia-
gram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at V
CC
±
0.3 V. Maximum V
CC
current is
reduced to 100 µA. The device enters the TTL-standby
mode when CE#/PGM# is at V
IH
. Maximum V
CC
cur-
rent is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-imped-
ance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
s
Low memory power dissipation, and
s
Assurance that output bus contention will not occur
CE#/PGM# should be decoded and used as the pri-
mary device-selecting function, while OE# be made a
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with V
PP
= 12.75 V
±
0.25 V will program
Am27C040
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
