SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
D
D
D
D
Processed to MIL-STD-883, Class B
Organization . . . 1 048 576
×
4
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
(tRAC) (tCAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
120 ns
30 ns
55 ns
210 ns
JDB OR HR PACKAGES
( TOP VIEW )
HL PACKAGE
( TOP VIEW )
D
SMJ44400-80
SMJ44400-10
SMJ44400-12
D
D
D
D
D
D
D
Enhanced Page-Mode Operation for Faster
Memory Access
– Higher Data Bandwidth Than
Conventional Page-Mode Parts
– Random Single-Bit Access Within a Row
With a Column Address
CAS-Before-RAS (CBR) Refresh
Long Refresh Period
1024-Cycle Refresh in 16 ms (Max)
3-State Unlatched Output
Low Power Dissipation
All Inputs / Outputs and Clocks are TTL
Compatible
Packaging Options:
– 20-Pin, 300-Mil Ceramic Side-Brazed DIP
(JDB suffix)
– 20-Pin Ceramic Flatpack (HR Suffix)
– 20-Pad, 350
×
675 Ceramic Chip Carrier
(HL suffix)
– 20-Pin Ceramic ZIP (SV suffix)
– Additional Package Options Planned
Military Temperature Range
– 55 to 125°C
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
1
2
3
4
5
26
25
24
23
22
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
9
10
11
12
13
18
17
16
15
14
SV PACKAGE
( TOP VIEW )
OE
DQ3
V
SS
DQ2
RAS
AO
A2
V
CC
A5
A7
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
CAS
DQ4
DQ1
W
A9
A1
A3
A4
A6
A8
PIN NOMENCLATURE
A0 – A9
CAS
DQ1 – DQ4
OE
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
description
The SMJ44400 is a series of 4 194 304-bit dynamic random-access memories (DRAMs), organized as 1 048 576
words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and
low–power operation.
The SMJ44400 features maximum row access times of 80 ns, 100 ns, and 120 ns. Maximum power dissipation
is as low as 360 mW operating and 22 mW standby.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1995, Texas Instruments Incorporated
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1
SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
description (continued)
The SMJ44400 is offered in a 300-mil, 20-pin ceramic side-brazed dual-in-line package (JDB suffix), a 20-pin
ceramic flatpack (HR suffix), a 20-pad 350
×
675 ceramic chip carrier (HL suffix), and a 20-pin ceramic zig-zag
in-line package (SV suffix). All packages are characterized for operation from – 55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column addresses
A0 through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44400 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column address
can be presented immediately after row address hold time has been satisfied, usually well in advance of the
falling edge of CAS. In this case, data is obtained after t
CAC
maximum (access time from CAS low), if t
AA
maximum (access time from column address) has been satisfied. In the event that column addresses for the
next cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of t
CAC
or t
CPA
(access time from rising edge of CAS).
address (A0 – A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on inputs A0 through A9 and latched onto the chip by RAS. The ten column-address bits are set up on pins
A0 through A9 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges
of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS is used as a chip select, activating the output buffer as well as latching the address bits into the
column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle permitting a write operation independent of
the state of OE. This permits early-write operation to be completed with OE grounded.
data in / out (DQ1 – DQ4)
The high-impedance output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout
of two Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance
(floating) state until CAS and OE are brought low. In a read cycle the output becomes valid after all access times
are satisfied. The output remains valid while CAS and OE are low. CAS or OE going high returns it to the
high-impedance state.
2
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SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every 16 ms to retain data. This can be achieved by strobing
each of the1024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS (CBR) and hidden refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CSR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally. During CBR refresh cycles the
outputs remain in the high-impedance state.
HIdden refresh can be performed while maintaining valid data at the output pins. This is accomplished by
holding CAS at V
IL
after a read operation. RAS is cycled after the specified read cycle parameters are met.
HIdden refresh can also be used in conjunction with an early-write cycle. CAS is maintained at V
IL
while RAS
is cycled, once all the specified early-write parameters are met. Externally generated addresses must be used
to specify the location to be accessed during the initial RAS cycle of a hidden refresh operation. Subsequent
RAS cycles (refresh cycles) use the internally-generated addresses and the external address is ignored.
power up
To achieve proper device operation, an initial pause of 200
µs
followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CBR) cycle.
test mode
An industry standard Design For Test (DFT) mode is incorporated in the SMJ44400. A CBR with W low (WCBR)
cycle is used to enter test mode. In the test mode, data is written into and read from eight sections of the array
in parallel. All data is written into the array through DQ1. Data is compared upon reading and if all bits are equal,
all DQ pins go high. If any one bit is different, all the DQ pins go low. Any combination read, write, read-write,
or page-mode can be used in the test mode. The test mode function reduces test times by enabling the
1M
×
4-bit DRAM to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only or
CBR refresh cycle is used to exit the DFT mode.
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3
SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
logic symbol
†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
9
10
11
12
14
15
16
17
18
5
RAM 1024K
×
4
20D10/21D0
A
0
1 048 575
RAS
4
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
23
3
22
1
2
24
25
20D19/21D9
C20[Row]
G23/[Refresh Row]
24[Power Down]
C21[Column]
G24
&
23,21D
G25
A,22D
26
23C22
24,25EN
A,Z26
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the HL package.
functional block diagram
RAS
CAS
W
OE
Timing and Control
A0
A1
Column
Address
Buffers
A9
2
8
Column Decode
Sense Amplifiers
128K Array
128K Array
R
o
w
D
e
c
o
d
e
128K Array
10
128K Array
128K Array
128K Array
16
16
16
16
Row
Address
Buffers
I/O
Buffers
4 of 16
Selection
2
Data
In
Reg.
Data
Out
Reg.
4
4
10
DQ1 – DQ4
4
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SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
absolute maximum ratings over operating temperature range (unless otherwise noted)
†
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
VCC
VIH
VIL
TA
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Minimum operating temperature
4.5
2.4
–1
– 55
NOM
5
MAX
5.5
6.5
0.8
UNIT
V
V
V
°C
TC
Maximum operating case temperature
125
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VOH
VOL
II
IO
ICC1
ICC2
High-level output voltage
Low-level output voltage
Input current (leakage)
Output current (leakage)
Read- or write-cycle
current (see Note 3)
Standby current
TEST CONDITIONS
IOH = – 5 mA
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All other pins = 0 V to VCC
VCC = 5.5 V,
CAS high
VCC = 5.5 V,
VO = 0 V to VCC,
’44400-80
MIN
2.4
0.4
±
10
±
10
85
MAX
’44400-10
MIN
2.4
0.4
±
10
±
10
80
MAX
’44400-12
MIN
2.4
0.4
±
10
±
10
70
MAX
UNIT
V
V
µA
µA
mA
Minimum cycle
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
VCC = 5.5 V,
RAS low,
tPC = minimum,
CAS cycling
4
4
4
mA
ICC3
Average refresh current
(RAS only, or CBR)
(see Note 3)
Average page current
(see Note 4)
85
75
65
mA
ICC4
50
40
35
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
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