Am42DL640AH
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
30774
Revision
A
Amendment
+1
Issue Date
December 5, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am42DL640AH
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.3 volt
■
High performance
— Access time as fast as 70 ns flash/55 ns SRAM
■
Minimum 1 million write cycles guaranteed per sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Package
— 73-Ball FBGA
■
Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Supports Common Flash Memory Interface (CFI)
■
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Flexible Bank™ architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■
Manufactured on 0.17 µm process technology
■
SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Boot sectors
— Top and bottom boot sectors in the same device
■
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
SRAM Features
■
Power dissipation
— Operating: 30 mA maximum
— Standby: 20 µA maximum
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
CE1s# and CE2s Chip Select
■
Power down features using CE1s# and CE2s
■
Data retention supply voltage: 1.5 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
30774
Rev:
A
Amendment/+1
Issue Date:
December 5, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
Am29DL640H Features
The Am29DL640H is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words of 16
bits each. Word mode data appears on DQ15–DQ0.
The device is designed to be programmed in-system
with the standard 3.0 volt V
CC
supply, and can also be
programmed in standard EPROM programmers.
The device is available with an access time of 70 or 85
ns and is offered in a 73-ball FBGA package. Standard
control pins—chip enable (CE#f), write enable (WE#),
and output enable (OE#)—control normal read and
write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s ys te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into
four banks,
two 8 Mb banks with small and
large sectors, and two 24 Mb banks of large sectors
only. Sector addresses are fixed, system software can
be used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL640H offers top and bottom boot sectors
in the same device. Thus, the host system can config-
ure and use the device as required..
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
8 Mb
24 Mb
24 Mb
8 Mb
Sector Sizes
Eight 4 Kword,
Fifteen 32 Kword
Forty-eight 32 Kword
Forty-eight 32 Kword
Eight 4 Kword,
Fifteen 32 Kword
The
SecSi™ (Secured Silicon) Sector
is an extra
256 byte sector capable of being permanently locked
by AMD or customers. The SecSi Customer Indicator
Bit (DQ6) is permanently set to 1 if the part has been
customer locked, permanently set to 0 if the part has
been factory locked, and is 0 if customer lockable. This
way, customer lockable parts can never be used to re-
place a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
2
Am42DL640AH
December 5, 2003
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package .................... 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29DL640H Sector Architecture ....................................11
Table 3. Bank Address ....................................................................14
Table 4. SecSi™ Sector Addresses ...............................................14
Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32
Figure 8. Maximum Negative Overshoot Waveform ...................... 32
Figure 9. Maximum Positive Overshoot Waveform........................ 32
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
CMOS Compatible .................................................................. 33
SRAM DC and Operating Characteristics . . . . . 34
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 35
Figure 11. Typical I
CC1
vs. Frequency ............................................ 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Test Setup.................................................................... 36
Figure 13. Input Waveforms and Measurement Levels ................. 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
SRAM CE#s Timing ................................................................ 37
Figure 14. Timing Diagram for Alternating
Between SRAM to Flash ................................................................ 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Flash Read-Only Operations ................................................. 38
Figure 15. Read Operation Timings ............................................... 38
Hardware Reset (RESET#) .................................................... 39
Figure 16. Reset Timings ............................................................... 39
Write Protect (WP#) ................................................................ 15
Table 6. WP#/ACC Modes ..............................................................16
Word/Byte Configuration (CIOf) .............................................. 40
Figure 17. CIOf Timings for Read Operations................................ 40
Figure 18. CIOf Timings for Write Operations................................ 40
Temporary Sector Unprotect .................................................. 16
Figure 1. Temporary Sector Unprotect Operation........................... 16
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 17
Erase and Program Operations .............................................. 41
Figure 19. Program Operation Timings..........................................
Figure 20. Accelerated Program Timing Diagram..........................
Figure 21. Chip/Sector Erase Operation Timings ..........................
Figure 22. Back-to-back Read/Write Cycle Timings ......................
Figure 23. Data# Polling Timings (During Embedded Algorithms).
Figure 24. Toggle Bit Timings (During Embedded Algorithms)......
Figure 25. DQ2 vs. DQ6.................................................................
42
42
43
44
44
45
45
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 18
Figure 3. SecSi Sector Protect Verify.............................................. 19
Hardware Data Protection ...................................................... 19
Low V
CC
Write Inhibit ........................................................... 19
Write Pulse “Glitch” Protection ............................................ 19
Logical Inhibit ...................................................................... 19
Power-Up Write Inhibit ......................................................... 19
Common Flash Memory Interface (CFI) . . . . . . . 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ..
23
Program Command Sequence ............................................... 24
Unlock Bypass Command Sequence .................................. 24
Figure 4. Program Operation .......................................................... 25
Temporary Sector Unprotect .................................................. 46
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 47
Alternate CE#f Controlled Erase and Program Operations .... 48
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 49
SRAM Read Cycle .................................................................. 50
Figure 29. SRAM Read Cycle—Address Controlled...................... 50
Figure 30. SRAM Read Cycle ........................................................ 51
SRAM Write Cycle .................................................................. 52
Figure 31. SRAM Write Cycle—WE# Control ................................ 52
Figure 32. SRAM Write Cycle—CE1#s Control ............................. 53
Figure 33. SRAM Write Cycle—UB#s and LB#s Control ............... 54
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 25
Erase Suspend/Erase Resume Commands ........................... 26
Figure 5. Erase Operation............................................................... 26
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28
DQ7: Data# Polling ................................................................. 28
Figure 6. Data# Polling Algorithm ................................................... 28
Flash Erase And Programming Performance . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
Package Pin Capacitance. . . . . . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . .
55
55
55
55
56
DQ6: Toggle Bit I .................................................................... 29
Figure 7. Toggle Bit Algorithm......................................................... 29
Figure 34. CE1#s Controlled Data Retention Mode....................... 56
Figure 35. CE2s Controlled Data Retention Mode......................... 56
DQ2: Toggle Bit II ................................................................... 30
Reading Toggle Bits DQ6/DQ2 .............................................. 30
DQ5: Exceeded Timing Limits ................................................ 30
DQ3: Sector Erase Timer ....................................................... 30
Table 12. Write Operation Status ....................................................31
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLJ073—73-Ball Fine-Pitch Ball Grid Array .......................... 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
December 5, 2003
Am42DL640AH
3
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