3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ II
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 2MHz to 200MHz
Output frequency: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode
Lock indicator
Available in TQFP package
IDT5V995
DESCRIPTION:
The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V995 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through the
use of the DS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the
sOE
pin is held low, all the outputs are synchronously enabled.
However, if
sOE
is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V995 has
LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
PE
PD
sO E
TEST
FS
LO CK
REF
FB
3
DS1:0
3
1F1:0
/N
3
3
PLL
3
Skew
Select
1Q
0
1Q
1
3
3
2F1:0
3
Skew
Select
2Q
0
2Q
1
3
3F1:0
3
Skew
Select
3Q
0
3Q
1
3
4F1:0
3
Skew
Select
4Q
0
4Q
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2002
Integrated Device Technology, Inc.
FEBRUARY 2002
DSC 5851/6
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
REF
V
D D
GND
TEST
4F
0
3F
1
3F
0
2F
1
2F
0
1F
1
FS
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, V
DD
V
I
Description
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
T
STG
T
A
= 85°C
T
A
= 55°C
Max
–0.5 to +4.6
–0.5 to V
DD
+0.5
–0.5 to +5.5
0.7
1.1
–65 to +150
°C
Unit
V
V
V
W
44
4F
1
sOE
PD
PE
V
DD Q
V
DD Q
4Q
1
4Q
0
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1F
0
DS
1
DS
0
LOCK
V
DD Q
V
DD Q
1Q
0
1Q
1
GND
GND
GND
Storage Temperature Range
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
5
Max.
7
Unit
pF
13
14
15
16
17
18
19
20
21
22
V
DD Q
V
DD Q
3Q
1
V
DD Q
V
DD Q
3Q
0
2Q
1
GND
2Q
0
TQFP
TOP VIEW
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
sOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q
0
and 2Q
1
) in a LOW state (for PE = H) - 2Q
0
and 2Q
1
may
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
sOE
is HIGH, the nF[
1:0
] pins act as output
disable controls for individual banks when nF[
1:0
] = LL. Set
sOE
LOW for normal operation (has internal pull-down).
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
nF
[1:0]
FS
nQ
[1:0]
DS
[1:0]
PD
LOCK
V
DDQ
V
DD
GND
IN
IN
OUT
IN
IN
OUT
PWR
PWR
PWR
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
Four banks of two outputs with programmable skew
3-level inputs for feedback divider selection
Power down control. Shuts off entire chip when LOW (has internal pull-up).
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs.
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
PE
IN
NOTE:
1. When TEST = MID and
sOE
= HIGH, PLL remains active with nF[
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain in
effect unless nF[
1:0
] = LL.
GND
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF
[1:0]
, and DS
[1:0]
.
FB
2
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from 625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V995 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±7.8125ns
±67.5°
±18.75%
Example 1, F
NOM
= 25MHz
Example 2, F
NOM
= 37.5MHz
Example 3, F
NOM
= 50MHz
Example 4, F
NOM
= 75MHz
Example 5, F
NOM
= 100MHz
Example 6, F
NOM
= 150MHz
Example 7, F
NOM
= 200MHz
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
—
—
±7.8125ns
±135°
±37.5%
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
—
—
±7.8125ns
±270°
±75%
—
—
—
—
t
U
= 1.25ns
t
U
= 0.833ns
t
U
= 0.625ns
ns
Phase Degrees
% of Cycle Time
1/(32 x F
NOM
)
24 to 50MHz
FS = MID
1/(16 x F
NOM
)
48 to 100MHz
FS = HIGH
1/(8 x F
NOM
)
96 to 200MHz
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q
1:0
, 2Q
1:0
, and the
higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F
NOM
when the output connected to FB is undivided
and DS[
1:0
] = MM. The frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using a divided output as the
FB input and setting DS[
1:0
] = MM. Using the DS[
1:0
] inputs allows a different method for frequency multiplication (see Divide Selection Table).
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range
applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
3
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
DS [
1:0
]
LL
LM
LH
ML
MM
MH
HL
HM
HH
FB Divide-by-n
2
3
4
5
1
6
8
10
12
Permitted Output Divide-by-n connected to FB
(1)
1 or 2
1
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
1
NOTE:
1. Permissible output division ratios connected to FB. The frequency of the REF input will be F
NOM
/N when the part is configured for frequency multiplication by using an undivided
output for FB and setting DS[
1:0
] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
Skew (Pair #4)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Inverted
(2)
NOTES:
1. LL disables outputs if TEST = MID and
sOE
= HIGH.
2. When pair #4 is set to HH (inverted),
sOE
disables pair #4 HIGH when PE = HIGH,
sOE
disables pair #4 LOW when PE = LOW.
RECOMMENDED OPERATING RANGE
Symbol
V
DD
/V
DDQ
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
3
-40
Typ.
3.3
+25
Max.
3.6
+85
Unit
V
°C
4
IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
I
3
I
PU
I
PD
V
OH
V
OL
3-Level Input DC Current
(TEST, FS, nF
[1:0]
, DS
[1:0]
)
Input Pull-Up Current (PE,
PD)
Input Pull-Down Current (sOE)
Output HIGH Voltage
Output LOW Voltage
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
DD
or GND
V
DD
= Max.
V
IN
= V
DD
V
IN
= V
DD
/2
V
IN
= GND
V
DD
= Max., V
IN
= GND
V
DD
= Max., V
IN
= V
DD
V
DD
= Min., I
OH
=
−
2mA (LOCK Output)
V
DD
= Min., I
OL
= 2mA (LOCK Output)
V
DDQ
= Min., I
OL
= 12mA (nQ
[1:0]
Outputs)
V
DDQ
= Min., I
OH
=
−
12mA (nQ
[1:0]
Outputs)
HIGH Level
MID Level
LOW Level
—
+200
+50
—
—
+100
—
—
0.4
0.4
V
µA
µA
V
µA
Min.
2
—
V
DD
/2
−
0.3
—
V
DD
−
0.6
Max.
—
0.8
—
V
DD
/2+0.3
0.6
+5
Unit
V
V
V
V
V
µA
−
5
−
50
−
200
−
25
—
2.4
2.4
—
—
NOTE:
1. These inputs are normally wired to V
DD
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DD
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
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