Am49PDL640AG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
30049
Revision
A
Amendment
+5
Issue Date
November 20, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am49PDL640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and
16 Mbit (1 M x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.1 volt
■
High performance
— Access time as fast as 70 ns initial/ 25 ns subsequent
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
■
Package
— 73-Ball FBGA
■
Operating Temperature
— –25°C to +85°C
■
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
Flex Bank™ architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)
— Bank B: 24 Mbit (32 Kw x 48)
— Bank C: 24 Mbit (32 Kw x 48)
— Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■
Manufactured on 0.17 µm process technology
■
SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
■
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at V
CC
level
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Boot sectors
— Top and bottom boot sectors in the same device
■
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
Pseudo SRAM Features
■
Power dissipation
— Operating: 30 mA maximum
— Standby: 100 µA maximum
— Deep Power-down current: 10 µA
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 23 mA active read current
— 15 mA program/erase current
— 200 nA in standby or automatic sleep mode
■
CE1s# and CE2s Chip Select
■
Power down features using CE1s# and CE2s
■
Data retention supply voltage: 2.7 to 3.1 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■
Multiple pSRAM vendors available
■
Minimum 1 million write cycles guaranteed per sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 11/20/03
Publication#
30049
Rev:
A
Amendment/+5
Issue Date:
November 20, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29PDL640G Features
The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 4 Mwords. The device is offered in 73-ball
Fine-pitch BGA packages. The word-wide data (x16) ap-
pears on DQ15-DQ0. This device can be programmed
in-system or in standard EPROM programmers. A 12.0 V
V
PP
is not required for write or erase operations.
The device offers fast page access times of 25, 30, and 45
ns, with corresponding random access times of 65, 70, 85,
and 90 ns, respectively, allowing high speed microproces-
sors to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard.
Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume
feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides
simul-
taneous operation
by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the
completion of a program or erase operation, greatly improv-
ing system performance.
The device can be organized in both top and bottom sector
configurations. The banks are organized as follows:
Bank
A
B
C
D
Sectors
8 Mbit (4 Kw x 8 and 32 Kw x 15)
24 Mbit (32 Kw x 48)
24 Mbit (32 Kw x 48)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
Page Mode Features
The device is AC timing, input/output, and package
compat-
ible with 4 Mbit x16 page mode mask ROM.
The page size
is 8 words.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
Standard Flash Memory Features
The device requires a
single 3.0 volt power supply
(2.7 V
to 3.1 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
2
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6
PSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9
Random Read (Non-Page Read) ........................................ 11
Page Mode Read ................................................................ 11
Table 2. Page Select .......................................................................11
Word Program Command Sequence ...................................... 28
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation ......................................................... 29
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 5. Erase Operation.............................................................. 30
Simultaneous Operation ......................................................... 11
Table 3. Bank Select .......................................................................11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation .......................................... 12
Autoselect Functions ........................................................... 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 13
Table 4. Am29PDL640G Sector Architecture .................................13
Table 5. Bank Address ....................................................................14
Table 6. SecSi
TM
SectorSecure Sector Addresses .........................14
Table 7. Am29PDL640G Boot Sector/Sector Block Addresses for Pro-
tection/Unprotection ........................................................................15
Password Program Command ................................................ 30
Password Verify Command .................................................... 31
Password Protection Mode Locking Bit Program Command .. 31
Persistent Sector Protection Mode Locking Bit Program Com-
mand ....................................................................................... 31
SecSi Sector Protection Bit Program Command .................... 31
PPB Lock Bit Set Command ................................................... 31
DYB Write Command ............................................................. 31
Password Unlock Command .................................................. 32
PPB Program Command ........................................................ 32
All PPB Erase Command ........................................................ 32
DYB Write Command ............................................................. 32
PPB Lock Bit Set Command ................................................... 32
PPB Status Command ............................................................ 32
PPB Lock Bit Status Command .............................................. 32
Sector Protection Status Command ....................................... 32
Table 13. Memory Array Command Definitions ............................. 33
Table 14. Sector Protection Command Definitions ........................ 34
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 16
Persistent Sector Protection ................................................... 16
Persistent Protection Bit (PPB) ............................................ 16
Persistent Protection Bit Lock (PPB Lock) .......................... 16
Dynamic Protection Bit (DYB) ............................................. 16
Table 8. Sector Protection Schemes ...............................................17
Write Operation Status . . . . . . . . . . . . . . . . . . . . 35
DQ7: Data# Polling ................................................................. 35
Figure 6. Data# Polling Algorithm .................................................. 35
DQ6: Toggle Bit I .................................................................... 36
Figure 7. Toggle Bit Algorithm........................................................ 36
Persistent Sector Protection Mode Locking Bit ................... 17
Password Protection Mode ..................................................... 17
Password and Password Mode Locking Bit ........................ 18
64-bit Password ................................................................... 18
Write Protect (WP#) ................................................................ 18
Persistent Protection Bit Lock .............................................. 18
High Voltage Sector Protection .............................................. 19
Figure 1. In-System Sector Protection/
Sector Unprotection Algorithms ...................................................... 20
DQ2: Toggle Bit II ................................................................... 37
Reading Toggle Bits DQ6/DQ2 ............................................... 37
DQ5: Exceeded Timing Limits ................................................ 37
DQ3: Sector Erase Timer ....................................................... 37
Table 15. Write Operation Status ................................................... 38
pSRAM Power Down . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. State Diagram ................................................................. 39
Table 16. Standby Mode Characteristics ....................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 40
Figure 9. Maximum Negative Overshoot Waveform ...................... 40
Figure 10. Maximum Positive Overshoot Waveform...................... 40
Temporary Sector Unprotect .................................................. 21
Figure 2. Temporary Sector Unprotect Operation........................... 21
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region ................................................. 21
SecSi Sector Protection Bit ................................................. 22
Figure 3. SecSi Sector Protect Verify.............................................. 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. Test Setup.................................................................... 43
Figure 12. Input Waveforms and Measurement Levels ................. 43
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ......................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44
pSRAM CE#s Timing .............................................................. 44
Figure 13. Timing Diagram for Alternating
Between pSRAM to Flash .............................................................. 44
Read-Only Operations ........................................................... 45
Figure 14. Read Operation Timings ............................................... 45
Figure 15. Page Read Operation Timings...................................... 46
Hardware Reset (RESET#) .................................................... 47
Figure 16. Reset Timings ............................................................... 47
Erase and Program Operations .............................................. 48
Figure 17. Program Operation Timings.......................................... 49
Figure 18. Accelerated Program Timing Diagram.......................... 49
Figure 19. Chip/Sector Erase Operation Timings .......................... 50
November 20, 2003
Am49PDL640AG
3
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