IRFR110, IRFU110
Data Sheet
January 2002
4.7A, 100V, 0.540 Ohm, N-Channel Power
MOSFETs
These are N-Channel enhancement mode silicon gate
power field effect transistors designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These advanced
power MOSFETs are designed for use in applications such
as switching regulators, switching converters, motor drivers,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate-drive power.
These transistors can be operated directly from integrated
circuits.
Formerly developmental type TA17441.
Features
• 4.7A, 100V
• r
DS(ON)
= 0.540
Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• 175
o
C Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
IRFU110
IRFR110
PACKAGE
TO-251AA
TO-252AA
BRAND
IFU110
IFR110
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-251AA
SOURCE
DRAIN
GATE
JEDEC TO-252AA
GATE
SOURCE
DRAIN (FLANGE)
DRAIN (FLANGE)
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFR110, IRFU110
100
100
4.7
3.3
17
±
20
30
0.2
19
-55 to 175
300
260
UNITS
V
V
A
A
A
V
W
W/
o
C
mj
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Rating (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
TEST CONDITIONS
I
D
= 250
µ
A, V
GS
= 0V (Figure 10)
V
GS
= V
DS
, I
D
= 250
µ
A
V
DS
= Rated BV
DSS
, V
GS
= 0V
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V,
T
J
= 150
o
C
MIN
100
2
-
-
4.7
-
-
1.3
-
-
-
-
V
GS
= 10V, I
D
≈
5.6A, V
DS
= 0.8 x Rated BV
DSS
,
R
L
= 14
Ω
, I
G(REF)
= 1.5mA (Figure 14)
Gate Charge is Essentially Independent of Operat-
ing Temperature
V
GS
= 0V, V
DS
= 25V, f = 1.0MHz
(Figure 11)
-
-
-
-
-
-
Measured from the
Drain Lead, 6mm
(0.25in) from Package
to Center of Die
Measured from The
Source Lead, 6mm
(0.25in) from Header to
Source Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
D
L
D
G
L
S
S
TYP
-
-
-
-
-
-
0.41
2.0
7.6
24
14
14
5.2
1.5
2.2
180
82
15
4.5
MAX
-
4
25
250
-
±
100
0.540
-
11
36
21
21
7.7
-
-
-
-
-
-
UNITS
V
V
µ
A
µ
A
A
nA
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
nH
Drain to Source Breakdown Voltage
Gate to Threshold Voltage
Zero Gate Voltage Drain Current
On-State Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
(Note 4)
Forward Transconductance (Note 4)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Internal Drain Inductance
I
D(ON)
I
GSS
r
DS(ON)
g
fs
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
L
D
V
DS
> I
D(ON)
x r
DS(ON)MAX
, V
GS
= 10V
V
GS
=
±
20V
I
D
= 3.3A, V
GS
= 10V (Figures 8, 9)
V
DS
= 50V, I
DS
= 3.3A (Figure 12)
V
DD
= 50V, I
D
≈
5.6A, R
GS
= 24
Ω
, R
L
= 9.1
Ω
,
V
GS
= 10V
MOSFET Switching Times are Essentially Indepen-
dent of Operating Temperature
-
Internal Source Inductance
L
S
-
7.5
-
nH
Junction to Case
Junction to Ambient
R
θ
JC
R
θ
JA
Free Air Operation
-
-
-
-
5.0
110
o
C/W
o
C/W
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Source to Drain Diode Specifications
PARAMETER
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 2)
SYMBOL
I
SD
I
SDM
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse
P-N Junction Diode
D
MIN
-
-
TYP
-
-
MAX
4.7
17
UNITS
A
A
G
S
Source to Drain Diode Voltage (Note 4)
Reverse Recovery Time
Reverse Recovery Charge
NOTES:
V
SD
t
rr
Q
RR
T
J
= 25
o
C, I
SD
= 4.7A, V
GS
= 0V (Figure 13)
T
J
= 25
o
C, I
SD
= 5.6A, dI
SD
/dt = 100A/
µ
s
T
J
= 25
o
C, I
SD
= 5.6A, dI
SD
/dt = 100A/
µ
s
-
46
0.17
-
96
0.38
2.5
200
0.83
V
ns
µ
C
2. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
3. V
DD
= 25V, starting T
J
= 25
o
C, L = 1.3mH, R
G
= 25
Ω
, peak I
AS
= 4.7A.
4. Pulse test: pulse width
≤
300µs, duty cycle
≤
2%.
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
Unless Otherwise Specified
5
I
D
, DRAIN CURRENT (A)
0
4
3
2
1
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
Z
θ
JC
, TRANSIENT
THERMAL IMPEDANCE
0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
SINGLE PULSE
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JC
+ T
C
10
-3
10
-2
10
-1
1
10
0.01
10
-5
10
-4
t
1
, RECTANGULAR PULSE DURATION (s)
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Typical Performance Curves
10
2
Unless Otherwise Specified
(Continued)
10
T
C
= 25
o
C
T
J
= MAX RATED
SINGLE PULSE
10µs
100µs
1ms
V
GS
= 10V
I
D
, DRAIN CURRENT (A)
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
V
GS
= 8V
10
6
V
GS
= 7V
4
V
GS
= 6V
2
V
GS
= 5V
V
GS
= 4V
0
10
20
30
40
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
50
1.0
OPERATION IN THIS
AREA LIMITED
BY r
DS(ON)
0.1
1
10
10ms
DC
10
2
10
3
0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
10
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
V
GS
10V
I
D
, DRAIN CURRENT (A)
I
D
, DRAIN CURRENT (A)
8
V
GS
8V
6
V
GS
7V
4
V
GS
= 6V
2
V
GS
5V
0
0
2
4
6
V
GS
4V
8
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DS
≥
50V
1
T
J
= 175
o
C
T
J
= 25
o
C
0.1
10
-2
0
2
4
6
8
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V
r
DS(ON)
, DRAIN TO SOURCE
4
ON RESISTANCE (Ω)
2.4
3
1.8
I
D
= 3.3A
2
V
GS
= 10V
1
V
GS
= 20V
1.2
0.5
0
0
4
8
12
I
D
, DRAIN CURRENT (A)
16
20
0
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
IRFR110, IRFU110
Typical Performance Curves
1.25
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
1.15
C, CAPACITANCE (pF)
400
Unless Otherwise Specified
(Continued)
500
V
GS
= 0V, f = 1MHz
C
ISS
= CGS + CGD
C
RSS
= CGD
C
OSS
≈
CDS + CGS
1.05
300
C
ISS
C
OSS
100
C
RSS
0.95
200
0.85
0.75
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
0
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
2
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 10. DRAIN TO SOURCE BREAKDOWN VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
2.5
g
fs
, TRANSCONDUCTANCE (S)
2.0
T
J
= 25
o
C
1.5
T
J
= 175
o
C
1.0
I
SD
, SOURCE TO DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DS
≥
50V
10
2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
T
J
= 175
o
C
1.0
T
J
= 25
o
C
0.1
0.5
0
0
2
4
6
I
D
, DRAIN CURRENT (A)
8
10
0
0.4
0.8
1.2
1.6
2.0
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 5.6A
16
V
DS
= 80V
V
DS
= 50V
V
DS
= 20V
12
8
4
0
0
2
4
6
8
10
Q
g
, GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRFR110, IRFU110 Rev. B
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