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October 1999
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1-888
HC-55564/883
FN3738.1
Continuously Variable Slope
Delta-Modulator (CVSD)
The HC-55564/883 is a half duplex modulator/demodulator
CMOS intergrated circuit used to convert voice signals into
serial NRZ digital data and to reconvert that data into voice.
The conversion is by delta-modulation, using the
Continuously Variable Slope (CVSD) method of
modulation/demodulation.
While the signals are compatible with other CVSD circuits,
the internal design is unique. The analog loop filters have
been replaced by very low power digital filters which require
no external timing components. This approach allows
inclusion of many desirable features which would be difficult
to implement using other approaches.
The fundamental advantages of delta-modulation, along with
its simplicity and serial data format, provide an efficient (low
data rate/low memory requirements) method for voice
digitization. The device may be easily configured with the
National TP3040 PCM/CVSD filter.
The HC-55564/883 is usable from 9k bits/sec to above
64kbps. For more applications information, see Application
Notes AN576 and AN607.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of Para-
graph 1.2.1.Requires Few External Parts
• All Digital
• Requires Few External Parts
• Low Power Drain
• Time Constants Determined by Clock Frequency; No Cali-
bration or Drift Problems: Automatic Offset Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Control
• Automatic Overload Recovery
• Automatic “Quiet” Pattern Generation
• AGC Control Signal Available
Applications
• Voice Transmission Over Data Channels (Modems)
• Voice/Data Multiplexing (Pair Gain)
• Voice Encryption/Scrambling
• Voicemail
• Audio Manipulations: Delay Lines, Time Compression,
Echo Generation/Suppression, Special Effects, etc.
• Pagers/Satellites
• Data Acquisition Systems
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of Repro-
grammability
Ordering Information
PART
NUMBER
HC1-55564/883
HC4-55564/883
TEMPERATURE
RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PACKAGE
14 Lead CerDIP
20 Lead Ceramic LCC
Pinouts
HC-55564/883
(CERDIP)
TOP VIEW
HC-55564/883
(CLCC)
TOP VIEW
NC
DIGITAL
OUT
FZ
1 20 19
18 DIGITAL IN
17 NC
16 APT
15 NC
14 ENCODE/DECODE
13 CLOCK
9 10 11 12
NC
NC
NC
DIGITAL
GND
V
DD
V
DD
1
ANALOG GND 2
A
OUT
3
AGC 4
A
IN
5
NC 6
NC 7
14 DIG OUT
13 FZ
12 DIG IN
11 APT
10 ENC/DEC
9 CLOCK
8 DIG GND
ANALOG GND
3
2
A
OUT
4
NC 5
AGC 6
NC 7
A
IN
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HC-55564/883
Pin Description
PIN NO.
14 LEAD
DIP
1
2
3
PIN NO.
20 LEAD
LCC
2
3
4
SYMBOL
V
DD
Analog
GND
A
OUT
DESCRIPTION
Positive Supply Voltage. Voltage range is +3.2V to +6.0V.
Analog Ground connection to D/A ladders and comparator.
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 75kΩ source with DC offset of V
DD
/2. Within
±2dB
of Audio Input. Should be externally
AC coupled.
Automatic Gain Control output. A logic low level will appear at this output when the recovered signal ex-
cursion reaches one-half of full scale value. In each half cycle full scale is V
DD
/2. The mark-space ratio
is proportional to the average signal level.
Audio Input to comparator. Should be externally AC coupled. Presents approximately 200kΩ in series
with V
DD
/2.
No internal connection is made to these pins.
4
6
AGC
5
6, 7
8
1, 5, 7, 9,
10, 11, 15,
17
12
13
A
IN
NC
8
9
Digital
GND
Clock
Logic ground. 0V reference for all logic inputs and outputs.
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such that the
data is valid at the positive clock transition. In the encode mode, the digital data is clocked out on the
negative going clock transition. The clock rate equals the data rate.
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the logic
level applied to this input. A low level selects the encode mode, a high level the decode mode.
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, however;
internally the CVSD is still functional and a signal is still available at the A
OUT
port. Active low.
Input for the received digital NRZ data.
Force Zero input. Activating this input resets the internal logic and forces the digital output and the recov-
ered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the digital output at
1/2 the clock rate. When this is decoded by a receive CVSD, a 10mV
P-P
inaudible signal appears at audio
output. Active low.
Output for transmitted digital NRZ data.
10
11
12
13
14
16
18
19
Encode/
Decode
APT
Digital In
FZ
14
NOTE:
20
Digital Out
1. No active input should be left in a “floating condition”.
Functional Diagram
(1)
V
DD
3V TO 6V
(12)
DIGITAL
IN
V
DD
2
(10)
ENC/DEC
APT
(11) (13) FORCE
ZERO
RESET
T
D
Z
IN
(2)
ANALOG
GND
COMPARATOR
(9)
CLOCK
(8)
DIGITAL
GND
(14)
DIGITAL
OUT
3-BIT
SHIFT
REGISTER
F/F
Q
(5)
A
IN
10-BIT
DAC
10
10
RESET
6
STEP
SIZE
LOGIC
(3) A
OUT
(SIDE TONE)
Z
OUT
(4) AGC OUT
SIGNAL
ESTIMATE
FILTER 1ms
DIGITAL
MODULATOR
±1
SYLLABIC
FILTER
4ms
10-BIT
DAC
RESET
2
HC-55564/883
Absolute Maximum Ratings
Voltage at Any Pin . . . . . . . . . . . . . . . . . . .GND -0.3V to V
DD
+0.3V
Maximum V
DD
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Minimum V
DD
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.2V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300
o
C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V
Thermal Information
Thermal Resistance
θ
JA
θ
JC
o
C/W
CerDIP Package . . . . . . . . . . . . . . . . . . .
66
16
o
C/W
o
C/W
Ceramic LCC Package . . . . . . . . . . . . . .
65
15
o
C/W
o
C for T at
≤
+175
o
C
Package Power Dissipation Limit at +75
J
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.54W
Package Power Dissipation Derating Factor Above +75
o
C
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2W/
o
C
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 15.4W/
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Operating Supply Voltage (V
DD
Range)
. . . . . . . . . . . +3.2V
to
+6.0V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V
SUPPLY
= +5V, fclk = 16kHz, Operating Temperature = -55
o
C
≤
T
A
≤
+125
o
C, Unless Otherwise Specified.
GROUP A
SUBGROUP
1
2, 3
Logic Input High (Note 2)
V
IH
Input Level: ‘1’ = +3.5V,
‘0’ = +1.5V
Input Level: ‘1’ = +3.5V,
‘0’ = +1.5V
I
LOAD
= -40µA
1
2, 3
1
2, 3
1
2, 3
Logic Output Low (Note 3)
V
OL
I
LOAD
= +0.8mA
1
2, 3
Quieting Pattern
Amplitude (Note 8)
AGC Threshold (Note 9)
V
QP
FZ = 0; Clock Inputs
Switched Statically
Encode Mode
1
2, 3
1
2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
TYP
-
-
3.5
3.5
-
-
4.0
4.0
-
-
-
-
0.45
0.45
MAX
1.5
1.5
-
-
1.5
1.5
-
-
0.4
0.4
14
14
0.65
0.65
UNITS
mA
mA
V
V
V
V
V
V
V
V
mV
P-P
mV
P-P
F.S.
F.S.
PARAMETER
Supply Current
SYMBOL
I
DD
CONDITIONS
Encode Mode: A
IN
= 0V
Logic Input Low (Note 2)
V
IL
Logic Output High (Note 3)
V
OH
V
ATH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS
Devices Characterized at: V
DD
= +5.0V, T
A
= +25
o
C, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified.
LIMITS
PARAMETER
Sampling Rate
SYMBOL
CLK
CONDITIONS
A
IN
= 0.775 V
RMS
at 20Hz
A
IN
= 0.775 V
RMS
at
100Hz
NOTE
1, 12
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
CLK Duty Cycle
12
+25
o
C
+125
o
C, -55
o
C
TYP
9
9
30
30
MAX
64
64
70
70
UNITS
kBS
kBS
%
%
3
HC-55564/883
TABLE 3. ELECTRICL PERFORMANCE CHARACTERISTICS (Continued)
Devices Characterized at: V
DD
= +5.0V, T
A
= +25
o
C, Operating Temperature, fclk = 16kHz Clock Sampling Rate.
ENC/DDC = ENC = Encode Mode, Unless Otherwise Specified.
(Continued)
LIMITS
PARAMETER
Audio Input Voltage
SYMBOL
A
IN
A
OUT
Z
IN
CONDITIONS
A
IN
= 100Hz
A
IN
= 100Hz
A
IN
= 100Hz
NOTE
4, 12
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
Audio Output Voltage
5, 12
+25
o
C
+125
o
C, -55
o
C
Input Impedance
6, 12
+25
o
C
+125
o
C, -55
o
C
Output Impedance
Z
OUT
A
IN
= 100Hz
6, 12
+25
o
C
+125
o
C, -55
o
C
Transfer Gain
A
E-D
A
IN
= 0.775 V
RMS
at
100Hz
A
IN
at 100Hz. Note 8
11, 12
+25
o
C
-55
o
C, +125
o
C
12, 13
7, 12
10, 12
+25
o
C
+25
o
C
+25
o
C
TYP
-
-
-
-
150
150
35
35
-2
-2
0.3
0.10
0.70
MAX
1.2
1.2
1.2
1.2
500
500
25
25
+2
+2
-
0.14
0.90
UNITS
V
RMS
V
RMS
V
RMS
V
RMS
kΩ
kΩ
kΩ
kΩ
dB
dB
% of
Supply
% of
Supply
F.S.
Resolution
MIN Step Size
Clamping Threshold
NOTES:
RES
MSS
V
CTH
1. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the CVSD
on the positive going edge (see Figure 2). Clock may be run at less than 9kbps.
2. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
3. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V
DD
or ground; however, the short circuit duty cycle
must not exceed 5% in order to maintain an acceptable current density level. Digital data output is NRZ and changes with negative clock tran-
sitions. Each output will drive one LS TTL loads.
4. Recommended voice input range for best voice performance. Should be externally AC coupled.
5. May be used for side-tone in encode mode. Should be externally AC coupled.
6. Presents series impedance with audio signal. Zero signal reference is approximately V
DD
/2. Varies with audio input level by
±2dB.
7. The minimum audio output voltage change that can be produced by the internal DAC.
8. The “quieting” pattern or idle-channel audio output steps at 1/2 the bit rate, changing state on negative clock transitions.
9. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e. at V
DD
/2
±25%
of V
DD
.
10. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-scale val-
ue, and will unclamp when it falls below this value (positive or negative).
11. No load condition measured from audio in to audio out.
12. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are charac-
terized upon initial design release and upon design changes which would affect these characteristics.
13. The minimum audio input voltage above which encoding is guaranteed to take place.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
Interim Electrical Parameters (Pre Burn-In)
Final Electrical Test Parameters
Group A Test Requirements
Groups C and D Endpoints
NOTE:
1. PDA applies to Subgroup 1 only.
SUBGROUPS (SEE TABLE 1)
1
1 (Note 1), 2, 3
1, 2, 3
1
4
HC-55564/883
Die Characteristics
DIE DIMENSIONS:
82 x 147 x 20 ± 1 mils
METALLIZATION:
Type: AlSi
Thickness: 10kÅ ± 1kÅ
GLASSIVATION:
Type: Silane, 3% Phosphorous
Thickness: 13kÅ ± 2.6kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
TRANSISTOR COUNT:
1896
PROCESS: CMOS;
SAJI
Metallization Mask Layout
HC-55564/883
ANALOG
GND
V
DD
DIGITAL
OUT
FZ
A
OUT
DIGITAL IN
AGC
APT
ENC/DEC
A
IN
CLOCK
DIGITAL
GND
5
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