IDT54/74FCT823A/B/C
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
HIGH PERFORMANCE
CMOS BUS INTERFACE
REGISTER
IDT54/74FCT823A/B/C
FEATURES:
−
−
−
−
−
−
−
−
−
−
−
−
−
Equivalent to AMD’s Am29823 bipolar registers in pinout/function,
speed and output drive over full temperature and voltage supply
extremes
IDT54/74FCT823A equivalent to FAST™ speed
IDT54/74FCT823B 25% faster than FAST
IDT54/74FCT823C 40% faster than FAST
Buffered common Clock Enable (EN) and asynchronous Clear input
(CLR)
I
OL
= 48mA (commercial) and 32mA (military)
Clamp diodes on all inputs for ringing suppression
CMOS power levels (1mW typ. static)
TTL input and output compatibility
CMOS output level compatible
Substantially lower input current levels than AMD’s bipolar
Am29800 series (5µ A max.)
Military product compliant to MIL-STD-883, Class B
Available in the following packages:
•
Commercial: SOIC
•
Military: CERDIP, LCC, CERPACK
DESCRIPTION:
The FCT823 series is built using an advanced dual metal CMOS
technology. The FCT823 bus interface registers are designed to eliminate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear
(CLR) – ideal for parity bus interfacing in high-performance microprogram-
med systems.
The FCT823 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAM
D
0
14
D
N
EN
C LR
11
D
CL
Q
Q
D
CL
Q
Q
CP
CP
CP
13
OE
1
Y
0
Y
N
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1
c
2001 Integrated Device Technology, Inc.
AUGUST 2001
DSC-5426/1
IDT54/74FCT823A/B/C
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
D
1
OE
D
0
NC
Y
0
27
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
2
3
4
5
6
7
8
9
10
11
12
D24-1
SO24-2
E24-1
23
22
21
20
19
18
17
16
15
14
13
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
D
2
D
3
D
4
NC
D
5
D
6
D
7
5
6
7
8
9
10
11
4
3
2
1
28
26
25
24
23
Y
1
INDEX
V
CC
OE
1
24
V
CC
Y
2
Y
3
Y
4
NC
Y
5
Y
6
Y
7
L28-1
22
21
20
19
12
13
14
15
16
17
18
D
8
CLR
GND
NC
CP
CERDIP/ SOIC/ CERPACK
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial
–0.5 to +7
–0.5 to V
CC
0 to +70
–55 to +125
–55 to +125
0.5
120
Military
–0.5 to +7
–0.5 to V
CC
–55 to +125
–65 to +135
–65 to +150
0.5
120
Unit
V
V
°C
°C
°C
W
mA
8-link
LOGIC SYMBOL
9
D
D
Q
CP
CP
EN
CLR
OE
EN
CLR
9
Y
PIN DESCRIPTION
Name
D
I
CLR
I/O
I
I
Description
The D flip-flop data inputs.
For both inverting and non-inverting registers,
when the clear input is LOW and
OE
is LOW,
the Q
I
outputs are LOW. When the clear input is
HIGH, data can be entered into the register.
Clock Pulse for the Register; enters data into
the register on the LOW-to-HIGH transition.
The register three-state outputs.
Clock Enable. When the clock enable is LOW,
data on the D
I
input is transferred to the Q
I
output on the LOW-to-HIGH clock transition.
When the clock enable is HIGH, the Q
I
outputs
do not change state, regardless of the data or
clock input transitions.
Output Control. When the
OE
input is HIGH, the
Y
I
outputs are in the high impedance state.
When the
OE
input is LOW, the TRUE register
data is present at the Y
I
outputs.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed V
CC
by +.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
CP
Y
I
EN
I
O
I
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8-link
OE
I
NOTE:
1. This parameter is measured at characterization but not tested.
2
EN
Y
8
IDT54/74FCT823A/B/C
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE
Inputs
OE
H
H
H
L
H
L
H
H
L
L
CLR
H
H
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
D
I
L
H
X
X
X
X
L
H
L
H
(1)
Internal/
Outputs
Q
I
Y
I
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
NC
Z
Z
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Function
High Z
Clear
Hold
Load
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
Z = High Impedance
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
- 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V ± 5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ± 10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
OS
V
OH
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µ A
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300µ A
I
OH
= –15mA MIL.
I
OH
= –24mA COM'L.
V
CC
= 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µ A
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 300µ A
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L.
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
Input LOW Current
Off State (High Impedance)
Output Current
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
O
= V
CC
V
O
= 2.7V
V
O
= 0.5V
V
O
= GND
Min.
2
—
—
—
—
—
—
—
—
—
—
–75
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.3
4.3
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
–5
(4)
–5
10
10
(4)
–10
(4)
–10
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.5
0.5
V
V
mA
V
µA
Unit
V
V
µA
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
3
IDT54/74FCT823A/B/C
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
=
EN
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OE
=
EN
= GND
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
Min.
—
—
V
IN
≥
V
HC
V
IN
≤
V
LC
—
Typ.
(2)
0.2
0.5
0.15
Max.
1.5
2
0.25
Unit
mA
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
1.7
4
mA
—
2.2
6
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
V
IN
= 3.4V
V
IN
= GND
—
4
7.8
(5)
—
6.2
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT823A/B/C
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT823A
Test
Parameter
Description
PLH
t
Propagation Delay
t
PHL
CP to Y
I
(OE = LOW)
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(3)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
Com'l.
Mil.
IDT54/74FCT823B
Com'l.
Mil.
IDT54/74FCT823C
Com'l.
Mil.
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
Unit
—
—
4
2
4
2
—
6
7
6
10
20
—
—
—
—
14
—
—
—
12
23
7
8
—
—
4
2
4
2
—
7
7
7
—
—
—
—
11.5
20
—
—
—
—
15
—
—
—
13
25
8
9
—
—
3
1.5
3
0
—
6
6
6
—
—
—
—
7.5
15
—
—
—
—
9
—
—
—
8
15
6.5
7.5
—
—
3
1.5
3
0
—
6
6
6
—
—
—
—
8.5
16
—
—
—
—
9.5
—
—
—
9
16
7
8
—
—
3
1.5
3
0
—
6
6
6
—
—
—
—
6
12.5
—
—
—
—
8
—
—
—
7
12.5
6.2
6.5
—
—
3
1.5
3
0
—
6
6
6
—
—
—
—
7
13.5
—
—
—
—
8.5
—
—
—
8
13.5
6.2
6.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SU
t
H
t
SU
t
H
t
PHL
t
REM
t
W
t
W
t
PZH
t
PZL
Set-up Time HIGH or LOW DI to CP
Hold Time HIGH or LOW DI to CP
Set-up Time HIGH or LOW
EN
to CP
Hold Time HIGH or LOW
EN
to CP
Propagation Delay
CLR
to Y
I
Recovery Time
CLR
to CP
CP Pulse Width HIGH or LOW
CLR
Pulse Width LOW
Output Enable Time
OE
to Y
I
t
PHZ
t
PLZ
Output Disable Time
OE
to Y
I
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(3)
R
L
= 500Ω
C
L
= 5pF
(3)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
—
—
—
—
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
5
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